VHDL-FPGA-Verilog List Page 506

VHDL-FPGA-Verilog list

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AES Downloaded：0: A AES ALGORITHM
Date : 2025-06-20 Size : 869kb User : 华云
8BIT_CPU Downloaded：0: A CPU OF 8 BITS
Date : 2025-06-20 Size : 83kb User : 华云
A_CPU_verilog Downloaded：0: a cpu
Date : 2025-06-20 Size : 752kb User : 华云
VLSI_RISC_chip_disk Downloaded：0: a disk
Date : 2025-06-20 Size : 975kb User : 华云
barrel_shift Downloaded：0: This project si barrel shifter for an 8-bit
Date : 2025-06-20 Size : 2kb User : LEE
ADC_AD7490 Downloaded：0: THIS PROJECT IMPLEMENTED ON VITERX 4 FPGA and THE COMPLETE SOURCE FILES testbench, design file UCF file are there and THIS ADC is maily configured with SPI protocol interface SPI CLK,SPI DATA, SPI LE, the SPEED OF OPERAT
Date : 2025-06-20 Size : 762kb User : LEE
sicendianti Downloaded：0: Four layers of elevator control is realized by VHDL
Date : 2025-06-20 Size : 256kb User : 徐高兵
vhdlll Downloaded：0: VHDL realize frame synchronization barker code, contains a shift register, judgment, decoder.
Date : 2025-06-20 Size : 304kb User : 徐高兵
wcdma_4carrier_01151621 Downloaded：0: WCMDA8 carrier frequency system using a digital fiber optic repeater
Date : 2025-06-20 Size : 4.12mb User : eric
ddc_virtex5 Downloaded：0: V5-level inverter system used on the digital fiber optic repeater
Date : 2025-06-20 Size : 1.7mb User : eric
LCD12864_picture Downloaded：0: This is a program used for lcd12864 to show pictures,which using verilog.
Date : 2025-06-20 Size : 1.33mb User : zhijun
RISC_CPU Downloaded：0: This a verilog to write a simple RISC_CPU based state machine design, which contains various modules, each module through simulation without problems, the whole project tested on the board
Date : 2025-06-20 Size : 1.07mb User : 冯永帅

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