VHDL-FPGA-Verilog List Page 515

VHDL-FPGA-Verilog list

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freq Downloaded：0: verilog prepared frequency meter pin binding support Xilinx Spartan6
Date : 2025-08-28 Size : 4kb User :
sata_phy_latest.tar Downloaded：0: Phy written by verilog sata2 the physical layer, the lower layer can be applied to the interface control layer and sata2!
Date : 2025-08-28 Size : 378kb User : hezigang
szz Downloaded：0: CPLD-based digital clock, using VHDL language, the digital display, an adjustable transfer points, the whole point timekeeping function.
Date : 2025-08-28 Size : 287kb User : 李襄
Digital-dynamic-display-FPGA Downloaded：0: Digital dynamic display FPGA
Date : 2025-08-28 Size : 438kb User : zhouxiao
FPGA-PWM_LED Downloaded：0: FPGA to achieve LED PWM control routine
Date : 2025-08-28 Size : 429kb User : zhouxiao
des Downloaded：0: des algorithm Simple
Date : 2025-08-28 Size : 109kb User : kalyan
image_ver_main Downloaded：0: The design of multi level sensor is mostly based on FSM controller
Date : 2025-08-28 Size : 375kb User : kalyan
parallel_prefix_flag Downloaded：0: design of parallel prefix adder in verilog
Date : 2025-08-28 Size : 340kb User : kalyan
traffic_cntrl Downloaded：0: FSM based traffic light controller
Date : 2025-08-28 Size : 394kb User : kalyan
DDSN Downloaded：0: quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter
Date : 2025-08-28 Size : 1.79mb User : 连天
modelsim Downloaded：0: A used in spread spectrum communication system of CPLD program, basic QPSK modulation
Date : 2025-08-28 Size : 7kb User : 猫神
sdram_demo Downloaded：0: this file is to drive sdr sdram , it runs on platform successfully
Date : 2025-08-28 Size : 4.08mb User : 张绍龙

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