VHDL-FPGA-Verilog List Page 494

VHDL-FPGA-Verilog list

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a_vhd_16550_uart_latest.tar Downloaded：0: This core is designed to be a compatible with the National Semiconductor PC16550D UART (Universal Asynchronous Receiver/Transmitter).Some differences: The FIFO’s are always enabled Sticky Parity is not supported
Date : 2025-06-19 Size : 117kb User : 包
can_latest.tar Downloaded：0: Controller Area Network or CAN is a control network protocol Bosch that has found wide use in Industrial Automation and the Automotive Industry. Most of the patents of CAN are owned by Bosch and although there are no res
Date : 2025-06-19 Size : 1.12mb User : 包
ddr2_sdram_latest.tar Downloaded：0: 1. Init-Sequenz for the RAM 2. Automaic Write-Sequenz (writes 16 Datawords each 64Bit to the RAM) 3. Automatic Read-Sequenz (reads the first Dataword the RAM)
Date : 2025-06-19 Size : 3.41mb User : 包
wb_uart_latest.tar Downloaded：0: Implements a 16550/16750 UART. The UART core is fully based on another OpenCores project: UART_16750 by Sebastian Witt. Please find there the documentation regarding the Uart core. The interface is now compatible with a
Date : 2025-06-19 Size : 21kb User : 包
uart_latest.tar Downloaded：0: serial UART open source core. The design is engineered for use as a stand alone chip or for use with other of our cores. The reason for developing the Serial UART core is the fact, that asynchronous serial communication
Date : 2025-06-19 Size : 9kb User : 包
FPGA-SYSTEM-DESIGN-primer-EDK1-part1 Downloaded：0: FPGA SYSTEM DESIGN primer of EDK-1-part1.
Date : 2025-06-19 Size : 1.04mb User : lijainqiu
vga Downloaded：0: FPGA board universal VGA block
Date : 2025-06-19 Size : 1kb User : taldarin
OWIRE Downloaded：0: The code of 1wire bus
Date : 2025-06-19 Size : 333kb User : 陆伟
half_adder Downloaded：0: Written in their own half adder source code, you can directly import project, please download.
Date : 2025-06-19 Size : 241kb User : 曹明民
ddr_top Downloaded：0: ddr3 read and write
Date : 2025-06-19 Size : 2kb User : 冯鲲鹏
FPGA Downloaded：0: The code of XJTU s digital electronics experiment, wrote by Verilog.
Date : 2025-06-19 Size : 13.2mb User : fanxinkai
ram Downloaded：0: vhdl code for simple ram block
Date : 2025-06-19 Size : 1kb User : sanket

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