VHDL-FPGA-Verilog List Page 493

VHDL-FPGA-Verilog list

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TLC Downloaded：0: Vhdl code for traffic light controller
Date : 2025-06-19 Size : 1kb User : sanket
fifo_mem Downloaded：0: Synchronous FIFO, IP core generation ram, verified available.
Date : 2025-06-19 Size : 1kb User : Devin
adc7923 Downloaded：0: Complete the AD7923 control and data read, AD7923 as four-way AD, SPI output interface
Date : 2025-06-19 Size : 1kb User : 高飞
ds18b20 Downloaded：0: Complete chip DS18B20 single bus temperature sensor control and read, 16 bit parallel data coming
Date : 2025-06-19 Size : 2kb User : 高飞
test Downloaded：0: Minimum FPGA system test procedure, an LED flashing, an LED light, can complete the minimum system verification
Date : 2025-06-19 Size : 1kb User : 高飞
uart Downloaded：0: Serial port to send and receive procedures, can modify the baud rate, and the LED display data transceiver
Date : 2025-06-19 Size : 2kb User : 高飞
fenpin Downloaded：0: Dividing frequency division program, even, odd points frequency, duty cycle adjustable, the decimal frequency division
Date : 2025-06-19 Size : 1kb User : 高飞
FPGAPLJ Downloaded：0: FPGA frequency meter program, to achieve high a frequency count using LCD1602 display, to require the use of high frequency accuracy greatly help.
Date : 2025-06-19 Size : 11kb User : 黄兴
FPGA-51 Downloaded：0: FPGA and MCU combination to achieve frequency meter function, it can count on the accuracy of frequency, and to achieve the corresponding function, can complete technology and achieve frequency.
Date : 2025-06-19 Size : 58kb User : 黄兴
138 Downloaded：0: 138 decoder based on FPGA implementation can be achieved corresponding 3 line 8 line decoder function, suitable for beginners to use.
Date : 2025-06-19 Size : 563kb User : 黄兴
dds Downloaded：0: FPGA-based DDS program code can achieve powerful output sine wave, triangle wave, square wave waveform and frequency can be adjusted. Implement corresponding powerful.
Date : 2025-06-19 Size : 284kb User : 黄兴
Altera-Cyclone-V-Memory Downloaded：0: Altera Cyclone V FPGA ddr3 Memory control
Date : 2025-06-19 Size : 218kb User : jiajunxian

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