VHDL-FPGA-Verilog List Page 495

VHDL-FPGA-Verilog list

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Oscilloscope Downloaded：0: Basys 3 oscilloscope source code, can refer to.
Date : 2025-06-19 Size : 1.48mb User : 罗密
spi_flash_VHDL Downloaded：2: the chip is winbon w25p16. vhdl language. the sysclk is 125m. it is easy to jump to write , read, or erase status by change idle status.
Date : 2025-06-19 Size : 2kb User : 钱愈玉
my_second_fpga Downloaded：0: Using Quartus ii13.0 write binary adder, using the IP core RAM, and LCD display, open can be used directly.
Date : 2025-06-19 Size : 5.77mb User :
my_temp Downloaded：0: Using Quartus ii 13.0 reading project file written DS18B20 will read the results displayed on the LCD and stored in RAM.
Date : 2025-06-19 Size : 3.65mb User :
viterbi-decoder-verilog Downloaded：0: viterbi verilog implemetation based matlab
Date : 2025-06-19 Size : 1.04mb User : kim jan
practise Downloaded：0: FPGA experimental board design a digital stopwatch. According to subject the use of VHDL language to design a system, including the divider, switch debounce, enable control, counters, latches, and display the data select
Date : 2025-06-19 Size : 6.35mb User : 郑晓
OFDM_Convolution Downloaded：0: Write your own convolution code, simulation results can be achieved
Date : 2025-06-19 Size : 3.58mb User : yanhui
AD7606 Downloaded：0: AD7606 state machine drive, verilog code, can be normal use.
Date : 2025-06-19 Size : 3kb User : 小波
verilog_UART Downloaded：0: Verilog language FPGA serial transceiver module, I can receive can send also to change the baud rate
Date : 2025-06-19 Size : 345kb User : 张旭
Gluttonous-Snake Downloaded：0: Verilog language to write a game in which can run on the FPGA.
Date : 2025-06-19 Size : 1.22mb User : 张旭
FPGA_sent_UART Downloaded：0: Simple serial port to receive, transmit program that can send and receive, you can test by
Date : 2025-06-19 Size : 319kb User : chen
latticeECP3-serdes-test-code Downloaded：0: lattice ECP3 series high speed serdes test code
Date : 2025-06-19 Size : 5.17mb User : 崔佰顺

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