VHDL-FPGA-Verilog List Page 474

VHDL-FPGA-Verilog list

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16x2_lcd_display_driver_latest.tar Downloaded：0: verilog prepared by the LCD controller，It can be used as the development of LCD
Date : 2025-06-18 Size : 2kb User : 磊
my_sd_vga_test Downloaded：0: my_sd_vga_test, SD image file storage
Date : 2025-06-18 Size : 500kb User : 磊
04_div_clk_1Hz Downloaded：0: this a divide circuit module to get a plus signal of 1Hz
Date : 2025-06-18 Size : 3.1mb User : 刘年
08_counter_white Downloaded：0: this is a verilog file for counter
Date : 2025-06-18 Size : 2.96mb User : 刘年
02_buzzer Downloaded：0: this is a verilog file to driver the buzzer
Date : 2025-06-18 Size : 2.99mb User : 刘年
02_nonblocking_assignment Downloaded：0: this is a verilog HDL file for non blocking assignment.
Date : 2025-06-18 Size : 2.82mb User : 刘年
zhuangtaiji Downloaded：0: Verilog an interesting state machine case, simple and easy to understand. Suitable for beginners. Is a small game, sparten board available. Inclusion test.
Date : 2025-06-18 Size : 470kb User : 张家郡
test_rtls Downloaded：0: RTl hardware generation
Date : 2025-06-18 Size : 722kb User : ayaz
usb Downloaded：0: usb2.0 vhdl
Date : 2025-06-18 Size : 1kb User : rkl110
FPGA__source-code__Verilog Downloaded：0: Part of the basic functions of the source code for FPGA.Suitable for beginners to learn the simulation, the code readable, easy to understand, clear logic. Including triggers, full adder, divider, and parallel to serial
Date : 2025-06-18 Size : 1.82mb User : 张秋爽
ethcomm Downloaded：0: FPGA Ethernet Communications Interface
Date : 2025-06-18 Size : 366kb User : richard
state_machine Downloaded：0: Suitable for beginners.A simple state machine, there are eight state, digital tube output the serial number of the current state. Based on Mars- XC3S400-f experiment board
Date : 2025-06-18 Size : 1.42mb User : 龙晓磊

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