VHDL-FPGA-Verilog List Page 473

VHDL-FPGA-Verilog list

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test Downloaded：0: Test Pattern files used for testing on embedded development board
Date : 2026-01-01 Size : 1kb User : Jain
CRC Downloaded：0: Mode S transponder can be achieved in the process of inquiry AP domain encoding module, which is fully in accordance with the 260B protocol encoding
Date : 2026-01-01 Size : 3kb User : 赵强
Pre-Emphasis Downloaded：0: A novel approach to equalization of high-speed serial links combines both amplitude pre-emphasis to correct for intersymbol interference and phase pre-emphasis to compensate for deterministic jitter, in particular, data-
Date : 2026-01-01 Size : 7.26mb User : vel
VLSI4 Downloaded：0: The mismatch drift of dynamic circuits, which must be corrected by precharging before activation, is a fundamental process and device reliability issue for very large scale integration (VLSI) circuits. In this paper, we
Date : 2026-01-01 Size : 22.63mb User : vel
1 Downloaded：0: than dc parameter (saturation current, threshold voltage, etc.) degradation. An electron beam probing was performed on a 64-Mb DRAM chip to detect the influence of gate capacitance variation in dynamic circuit blocks bef
Date : 2026-01-01 Size : 19.95mb User : vel
2 Downloaded：0: for the first time, the impact of hotcarrier-induced gate capacitance variation on dynamic circuits in a VLSI chip. To investigate the mismatch drift due to the hot-carrier-induced gate capacitance variation, internal p
Date : 2026-01-01 Size : 12.09mb User : vel
sdram Downloaded：0: FPGA read SDRAM. There are detailed notes, reference for beginners,
Date : 2026-01-01 Size : 8.59mb User : 果粒橙
DDS Downloaded：0: FPGA to achieve three-channel DDS signal source Verilog program
Date : 2026-01-01 Size : 8.95mb User : 果粒橙
uart_rx Downloaded：0: Serial reception FPGA Verilog language
Date : 2026-01-01 Size : 3.12mb User : 果粒橙
uart_tx Downloaded：0: Serial reception FPGA Verilog language.
Date : 2026-01-01 Size : 3.16mb User : 果粒橙
basesignal Downloaded：0: Base band signal spectrum
Date : 2026-01-01 Size : 4kb User : 王先生
cpu Downloaded：0: VHDL to achieve the basic functions of the processor
Date : 2026-01-01 Size : 3kb User : 王先生

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