VHDL-FPGA-Verilog List Page 469

VHDL-FPGA-Verilog list

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uart_yll_pro Downloaded：0: CPLD The I2C communication, based on a modular design, verified on an oscilloscope
Date : 2025-06-18 Size : 475kb User : wop636
taxivalue Downloaded：0: I used the FPGA to achieve, this is a taxi meter, calculate the mileage, I have been in quartus 2 to achieve.
Date : 2025-06-18 Size : 3.21mb User : 宋冀生
cnt60 Downloaded：0: 60 counter
Date : 2025-06-18 Size : 178kb User : 武千魄
sheji2 Downloaded：0: Verilog-based digital thermometer with DS18B20 collecting temperature, serial communication interface with the computer via RS232
Date : 2025-06-18 Size : 4.67mb User : 方思
waterlights_fsm Downloaded：0: Using Verilog language, written in three-state machine to achieve water lights operating, it has been verified by test
Date : 2025-06-18 Size : 2.85mb User : 杨增健
asyn_fifo2 Downloaded：0: Using Verilog language, the use of FPGA IP core internal FIFO module, serial data transmission
Date : 2025-06-18 Size : 3.76mb User : 杨增健
PLL Downloaded：0: Using Verilog language, the use of IP cores PLL, produces three kinds of output at different frequencies, it has been verified by test
Date : 2025-06-18 Size : 3.03mb User : 杨增健
mouse_kit Downloaded：0: Adjustable implementation difficulty (6 level, different speeds) simple whack-a-mole game.The led lights on the development board represent mouse, key on behalf of the hammer.The program code can be directly d, suitable
Date : 2025-06-18 Size : 1.52mb User : 黄浩洸
VGAdisplay Downloaded：0: The system is written VHDL code for VGA protocol for control can be displayed on the display screen with a resolution of 640* 480, refresh rate of 60Hz and a color picture of color bar
Date : 2025-06-18 Size : 11.94mb User : 孙佳贝
dianzhen Downloaded：0: Lattice scanning procedures: need to achieve in sequence and cycle according to the dot matrix display effect, can be analyzed visually observed column changes, the scanning frequency of the column must be far less than
Date : 2025-06-18 Size : 711kb User : 丁明凯
add32 Downloaded：0: use 1 adders to be a 32 adder it is necessary for you to design a cpu
Date : 2025-06-18 Size : 107kb User : Richar
gpr Downloaded：0: made up of 32 regs be used to design single cpu
Date : 2025-06-18 Size : 102kb User : Richar

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