VHDL-FPGA-Verilog List Page 4260

VHDL-FPGA-Verilog list

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vhdl_vga Downloaded：0: color of the signal generator for use with the use of modules : VGA, pulse along the module, module clock source. Use steps : 1. Turn the power 5V 2. Signal connectivity, the table below will 1K30 signal with the actual
Date : 2025-05-14 Size : 93kb User : 刘浪
vhdl_LED Downloaded：0: lattice experimental use of the use of sample modules : clock source modules, dot-matrix display module, pulse along the module. Use steps : 1. Turn the power 5V. 2. Signal connectivity, the table below will 1K30 signal
Date : 2025-05-14 Size : 326kb User : 刘浪
Verilog_EXAMPLE Downloaded：0: Design Wave Verilog Example
Date : 2025-05-14 Size : 374kb User : sky
ddsall Downloaded：0: DDS source VHDL language to achieve the program can be realized 1HZ frequency Step
Date : 2025-05-14 Size : 1kb User : 欧阳
alu64_struct Downloaded：0: 64 ALU design source code can be modified to achieve, and logic, or other functions.
Date : 2025-05-14 Size : 1kb User : 李宁
相位差可调的双通道信号发生器的设计 Downloaded：0: phase difference adjustable dual-channel signal generator, we can use as a signal source
Date : 2025-05-14 Size : 302kb User : 胡路听
基于CPLD-FPGA的半整数分频器的设计 Downloaded：0: based CPLD-half FPGA integer dividers in the design, design for EDA
Date : 2025-05-14 Size : 21kb User : 胡路听
同步复位与异步复位问题 Downloaded：0: asynchronous and synchronous reset reduction, EDA application settings for beginners
Date : 2025-05-14 Size : 237kb User : 胡路听
用Verilog HDL实现I2C总线功能 Downloaded：1: with Verilog HDL I2C bus function of I2C bus is very helpful
Date : 2025-05-14 Size : 118kb User : 胡路听
dsfs Downloaded：0: scan signal from C0 to C3 into the signal in order of 1000-gt; 0100- gt; 0010- gt; 0001- gt; 1000 cycle, when the scanning signal to 1000, then scanning 0 line of four keys. Scanning signal for 0100, then scanning resolu
Date : 2025-05-14 Size : 110kb User : 杨要强
单片机坐标定时器实验 Downloaded：0: 7topic http://www.edacn.net/cgi-bin/forums.cgi forum = = 9127, under R3 R0 to the output signal will be one to one, but we are unable to confirm which a key is pressed, we must proceed from R3 to R0 the output signal C0
Date : 2025-05-14 Size : 1.49mb User : 杨要强
mp3if Downloaded：0: through CPLD to eight parallel data into serial data and methods can be used I2C connections with other devices, which can be used to provide MCU with I2C Interface Communications occasions.
Date : 2025-05-14 Size : 1kb User : hcguan

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