VHDL-FPGA-Verilog List Page 4257

VHDL-FPGA-Verilog list

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SRAM@DMA实验 Downloaded：0: Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Date : 2025-05-14 Size : 33kb User : xf
SPI接口音频Codec实验 Downloaded：0: Altera NIOS processor, the QUARTUS VHDL compiler, then the C language under NIOS SHELL-driven, experimental audio decoder
Date : 2025-05-14 Size : 34kb User : xf
frequency发生器 Downloaded：0: A frequency generator wirriten by VHDL, which can generate different frequecies.
Date : 2025-05-14 Size : 1kb User : xf
verilog hdl教程135例 Downloaded：0: Easy and simple VerilogHDL programs to help you to get to the language quickly.
Date : 2025-05-14 Size : 155kb User : 陈浩东
ASKDASK Downloaded：0: ask modulation, based on VHDL simulation platform, demodulator is the same, this procedure proven
Date : 2025-05-14 Size : 94kb User : we
FSKDFSK Downloaded：1: FSK modulation and demodulation, this procedure has been verified and can use communications students can use
Date : 2025-05-14 Size : 3kb User : we
lg Downloaded：0: they simply based on the logic analyzer can show that the Eighth Route Army waveform, real-time waveform analysis of the Eighth Route Army
Date : 2025-05-14 Size : 1kb User : 洪强
基于FPGA的李沙育图形发生器 Downloaded：0: This is a development with MAX PLUSII FPGA (1K30 device) developed Lissajous Pattern Generator (hardware description language).
Date : 2025-05-14 Size : 773kb User : 孔玉
32位-33M 从模式(target)PCI接口参考设计_lattice Downloaded：1: 32/route from the model (target) PCI reference design, Lattice provided. Because PCI timing more complicated, and the design for reference only
Date : 2025-05-14 Size : 807kb User : 陈旭
8051参考设计_Oregano System 提供_vhdl Downloaded：0: 8051 reference design, and other free IP in 8051 compared to relatively entire document, Oregano System for
Date : 2025-05-14 Size : 649kb User : 陈旭
CRC校验参考设计_xilinx_verilog Downloaded：0: IEEE 802.3 Cyclic Redundancy Check reference design for Xilinx
Date : 2025-05-14 Size : 88kb User : 陈旭
CRC校验参考设计_xilinx_vhdl Downloaded：0: configurable CRC reference design for Xilinx VHDL
Date : 2025-05-14 Size : 48kb User : 陈旭

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