VHDL-FPGA-Verilog List Page 4259

VHDL-FPGA-Verilog list

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I2C总线控制器 Xilinx提供 Downloaded：0: I2C bus contrll functions implemented by Verilog HDL.
Date : 2025-05-14 Size : 869kb User : 司法
lightW Downloaded：0: a small LCD lights procedures. I did not write. I am only responsible for the debugging. Apply in ACEXEP1K30QC208-3 on. I run a simulator, marking the connecting pin. I next tried in a circuit board, there is no problem.
Date : 2025-05-14 Size : 231kb User : 鄧翀
intro_to_quartus2_chinese Downloaded：0: A Chinese introduction to quartus II.
Date : 2025-05-14 Size : 2.95mb User : 石峰
Figure_Models Downloaded：0: James Armstrong VHDL Design , source code
Date : 2025-05-14 Size : 45kb User : 真名
des-verilog Downloaded：1: des encryption algorithm to achieve the Verilog language
Date : 2025-05-14 Size : 66kb User : 杨云丰
clock_time Downloaded：0: this document unpacked clock_time.vhd maxplusII use programming environment, the time for completion seconds timing, Hutchison, the set-up time seconds, sound, light, alarm functions.
Date : 2025-05-14 Size : 1kb User : 阿兰
示例（vhdl） Downloaded：0: VHDL examples examples to learn VHDL programming
Date : 2025-05-14 Size : 76kb User : joan
UART设计参考 Downloaded：0: software designers Watchable UART reference design
Date : 2025-05-14 Size : 93kb User : joan
ClkScan Downloaded：0: This design uses Verilog the HDL hardware language design, realizes on the palm space development board Divides into two stature modules the entire electric circuit, provides the synchronized signal (H_SYNC and V_SYNC)
Date : 2025-05-14 Size : 896kb User :
qdq_new Downloaded：0: Uses Verilog the HDL design, obtains the realization basis on the palm space intelligence development board to snatch the answering principle, the entire electric circuit may divide is three parts: The sampling electric
Date : 2025-05-14 Size : 64kb User :
second&clk Downloaded：0: Development system using the clock signal frequency is 20MHz, the design can be counter to its count, including seconds, minutes, hours, days, weeks, months and years. At every level to show the output, thus constitutes
Date : 2025-05-14 Size : 329kb User :
Music_altera Downloaded：0: Uses Verilog the HDL design, development board realizes in Altera on the EP1S10S780C6 selects 6MHz is the datum frequency, the performance is Liang wishes the music
Date : 2025-05-14 Size : 637kb User :

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