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VHDL-FPGA-Verilog list
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algorithm using the symbols multiplier, HDL-piece quantities. it is not necessary for the company's paid Multiplier ip core.
Date : 2025-05-17 Size : 2kb User : 蒋雯丽

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Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!
Date : 2025-05-17 Size : 3kb User : 李全

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an analog video input to VGA video output Verilog procedures, Video decoder chip used ADV7181B, VGA DAC used ADV7123, strongly recommended!
Date : 2025-05-17 Size : 26kb User : 李全

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HDL programming style, very useful, we want to help.
Date : 2025-05-17 Size : 24kb User : 张丰

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FPGA/CPLD applications, UART communications VHDL source.
Date : 2025-05-17 Size : 10kb User : cyberworm

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FPGA/CPLD applications, UART Verilog HDL source
Date : 2025-05-17 Size : 10kb User : cyberworm

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ModelSim waveform can be compared to the current functional simulation with a reference (WLF paper ), the results can be compared in the waveform window or window List View, it will also compare the results generate a te
Date : 2025-05-17 Size : 3kb User : cyberworm

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prepared using VHDL code for all to study and exchange to facilitate learning!
Date : 2025-05-17 Size : 4kb User : 和尚

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prepared using VHDL code for all to study and exchange to facilitate learning!
Date : 2025-05-17 Size : 26kb User : 和尚

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This a voice procedures, through a VHDL compiler. you can directly call. It also includes a keyboard procedures need to look at it down
Date : 2025-05-17 Size : 166kb User : 李飞

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using Verilog cpld written by the various sub-frequency procedures in the hope that we stand corrected, thank you!
Date : 2025-05-17 Size : 1kb User : 沈柱

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FPGA and DSP EMIFA mouth interface program. The FPGA distribution within the two-SUBJECT ER and DSP communication.
Date : 2025-05-17 Size : 7kb User : tanbo
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