VHDL-FPGA-Verilog List Page 4207

VHDL-FPGA-Verilog list

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digitalsystemDesign Downloaded：0: Chapter 7 Digital System Design Example 7.1-integer dividers designed Music Generator 7.2 7.3 2F SK/2PSK Signal Generator 7.4 Table practical multi-function electronic traffic signal controllers 7.5 7.6 Digital Cymometer
Date : 2025-05-17 Size : 436kb User : 李唐
statemachine Downloaded：0: doing more of a state machine on the three described earlier. Many more information, please everyone's attention.
Date : 2025-05-17 Size : 793kb User : 潘应云
u-uart Downloaded：0: a comprehensive series of conversion and interface Verilog source code
Date : 2025-05-17 Size : 5kb User : 李文文
CORDIC01 Downloaded：0: CORDIC algorithm Hardware Implementation of the Verilog language
Date : 2025-05-17 Size : 216kb User : 李文文
ethernet[1].tar Downloaded：0: an Ethernet card hardware description, reference card chip design.
Date : 2025-05-17 Size : 141kb User : 李文文
Cpu_model Downloaded：0: Verilog HDL prepared by the CPU model, classic, more generic
Date : 2025-05-17 Size : 1kb User : wyl
bfm Downloaded：0: Verilog HDL prepared by the bus functional model is useful, it needs to download
Date : 2025-05-17 Size : 2kb User : wyl
whole_clock_code Downloaded：0: an electronic experiments of Verilog source code. Suitable for beginners learning Verilog reference
Date : 2025-05-17 Size : 165kb User : dandan
de2_clock Downloaded：0: for Dictyophora board, in the way of achieving LCD clock function.
Date : 2025-05-17 Size : 79kb User : 曾
user_logic_VGA_Controller Downloaded：0: user_logic_VGA_Controller. suitable for Dictyophora development board, this folder on the project directory, it can be added directly SOPC Lane VGA_Controller IP core, very convenient to use.
Date : 2025-05-17 Size : 69kb User : 曾
Ivga Downloaded：0: VHDL write calculators, Modified functions and achieve VGA display, VHDL for beginners.
Date : 2025-05-17 Size : 480kb User : yumen
8LEDverilog Downloaded：0: //led.v /*------------------------------------- LED Display Module : led (CLK, AF, ADDR. DATA) function : to show : 8 LED parameters : CLK : So Wonderful clock input, Suggest 1kHz AF : digital tube output, a ~ h ADDR : d
Date : 2025-05-17 Size : 1kb User : 黄道斌

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