VHDL-FPGA-Verilog List Page 4204

VHDL-FPGA-Verilog list

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RS_decoder Downloaded：0: rs coding vvhdl I do not want to be able to know the specific useful whether you want to understand a lot of coding rs exchange
Date : 2025-05-17 Size : 15kb User :
I2CSlave Downloaded：0: achieve the Verilog HDL simulation I2C Slave
Date : 2025-05-17 Size : 1kb User : lzy
lru_new Downloaded：0: using LRU replacement algorithm. This algorithm to choose the most long visit is not being replaced as a block by block. To achieve LRU algorithm, in block form for each one to set up a Counter (cnt0, cnt1. cnt2, cnt3,).
Date : 2025-05-17 Size : 1kb User : wangjiao
ls12_mux16 Downloaded：0: A 16-bit multiplier veriolog language. Use a novice.
Date : 2025-05-17 Size : 959kb User : 1412
I2C_1.1 Downloaded：0: Simple I2C controller-- 1) No multimaster-- 2) No slave mode-- 3) No fifo's---- notes :-- Every command is acknowledged. Do not set a ne w command before previous is acknowledged.-- D is available out a clock cycle later
Date : 2025-05-17 Size : 3kb User : 郑开科
tst_ds1621 Downloaded：0: -- State machine for reading data from Dall as 1621---- Testsystem for i2c controller
Date : 2025-05-17 Size : 2kb User : 郑开科
wishbone_i2c_master Downloaded：0: -- WISHBONE revB2 compiant I2C master core---- author : Richard Herveille-- rev. 0.1 based on simple_i 2c-- rev. 0.2 adolescence 27th 2001, fixed incomplete sensitivity list on assign_d ato process (thanks to Matt Oseman
Date : 2025-05-17 Size : 5kb User : 郑开科
add_sub_lab2 Downloaded：0: experiment include the operation of a half adder, full adder, plus/subtraction device, and the use of logic diagram VHDl description, including analysis and reporting.
Date : 2025-05-17 Size : 59kb User : 徐轶尊
110detector_lab Downloaded：0: a simple survey of 110 three detectors, and a logical map vhdl description, including reports and experimental test plan.
Date : 2025-05-17 Size : 140kb User : 徐轶尊
2460100Time Downloaded：0: 24,60,100 229 of the counter, digital clock also welcome to download oh ~
Date : 2025-05-17 Size : 2kb User : 张春
addersubtractor Downloaded：0: This is vhdl prepared by the modified instruments used in the 16bit
Date : 2025-05-17 Size : 1kb User : 马永涛
cpld1380 Downloaded：0: a good VHDL functional module procedures in the hope that you can use!
Date : 2025-05-17 Size : 1kb User : 王涛

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