VHDL-FPGA-Verilog List Page 4200

VHDL-FPGA-Verilog list

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yimazhenque Downloaded：0: 47 decoder for verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Date : 2025-05-17 Size : 21kb User : 刘东辉
lpm_mul Downloaded：0: 8* 8 Multiplier verilog source code, compiled simulation, absolute authenticity, helpful for beginners
Date : 2025-05-17 Size : 27kb User : 刘东辉
binary2bcd Downloaded：0: This build is for developing a "binary-to- BCD "converter for use in// displaying numeral 's in base-10 so that people can read and interpre not the// numbers more readily than they could if t he numbers were displayed i
Date : 2025-05-17 Size : 41kb User : 陈朋
DaFilter Downloaded：0: /* This program generates the DApkg.vhd fi le that is used to define the DA* filter core and g ives its parameters and the contents of the Dis* tributed Arithmetic Look-up-table "DALUT" ac cording to the DA algorithm
Date : 2025-05-17 Size : 15kb User : 陈朋
DCT_vhdl Downloaded：0: IDCT-M is a medium speed 1D IDCT core-- it ca n accept a continuous stream of 12-bit input word 's at a rate of-- 1 bit/ck cycle, operating at 50MHz speed, it can process MP @ ML MPEG video-- the core is 100 % synthesiza
Date : 2025-05-17 Size : 10kb User : 陈朋
Shifters_vhdl Downloaded：0: -- Title : Barrel Shifter (Pure combinational)-- This VH DL design file is an open design you can redistri bute it and/or-- modify it and/or implement it a fter contacting the author-- You can check the d raft license at
Date : 2025-05-17 Size : 2kb User : 陈朋
cf_interleaver2 Downloaded：0: interleaver that interleaver, which contains C, VHDL, VRILOG HDL three languages to write the interleaver, including a variety of combinations to depend species, a detailed description, is a rare study of the materials a
Date : 2025-05-17 Size : 352kb User : 陈朋
mdct.tar Downloaded：0: This April 06 had just completed the process, from opencore.org downloaded from. Vhdl description language used, and Matlab simulation, testbench, and the Comprehensive xinlinx. The MDCT core is two dimensional discrete
Date : 2025-05-17 Size : 1.69mb User : 陈朋
fpu_v18 Downloaded：0: fpupack.vhdpre_norm_addsub.vhdaddsub_28.vhdpost_norm_addsub.vhdpre_norm_mul.vhdmul_24.vhdvcom serial_mul.vhdpost_norm_mul.vhdpre_norm_div.vhdserial_div.vhdpost_norm_div.vhdpre_norm_sqrt.vhdsqrt
Date : 2025-05-17 Size : 466kb User : 陈朋
System09 Downloaded：0: BurchED B5- X300 Spartan2e using XC2S300e Top level device file for 6809 compatible syste m on a chip Designed with Xilinx XC2S300e Sparta n 2 FPGA. Implemented With BurchED B5- X300 FPGA board, B5-SRAM module, B5-CF mod
Date : 2025-05-17 Size : 596kb User : 陈朋
xljc Downloaded：0: Sequence Detection VHDL source code, ATERA platform compile. Report detailed description and simulation of the source code.
Date : 2025-05-17 Size : 12kb User : 孙彬
VerilogHDLICdesign Downloaded：0: proficient VerilogHDL : IC design example explanation of the core technology
Date : 2025-05-17 Size : 509kb User : haha

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