VHDL-FPGA-Verilog List Page 4169

VHDL-FPGA-Verilog list

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Synthesisofverilog Downloaded：0: a useful comprehensive Verilog language study
Date : 2025-05-19 Size : 266kb User : wrrkaixin
2006829121816 Downloaded：0: simple logic analyzer with the design of the source code for electronic 05 2 Prize Competition works
Date : 2025-05-19 Size : 198kb User : 邓勇
9.1_ONE_PULSE Downloaded：0: based on Verilog-HDL hardware Circuit of 9.1 simple programmable pulse generator 9.1.1 system functions described by the temporal flow chart 9.1.2 9.1.3 System Design Description logic diagram 9.1.5 9.1.4 Delay Module de
Date : 2025-05-19 Size : 4kb User : 宁宁
9.2_LCD_PULSE Downloaded：0: based on Verilog-HDL hardware Circuit of 9.2 LCD display module with the series Single-Pulse Generator 9.2.1 LCD display module Principle 9.2.2 shows the logic design Thinking and Process 9.2.3 LCD display module hardwar
Date : 2025-05-19 Size : 5kb User : 宁宁
9.3_Pulse_Counter Downloaded：0: based on Verilog-HDL hardware Circuit of 9.3 pulse count and showed 9.3 .1 pulse counter the principle 9.3.2 Counting Module Design and Implementation para 9.3.3 meter usage 9.3.4 repeat cycle statement on the use 9.3.5-
Date : 2025-05-19 Size : 4kb User : 宁宁
9.4_PULSE_FRE Downloaded：0: based on Verilog-HDL hardware Circuit of 9.4 pulse frequency measurement and display 9.4.1 pulse frequency measurement frequency 9.4.2 principle, the principle 9.4.3 Frequency Measurement Module Design and Implementation
Date : 2025-05-19 Size : 2kb User : 宁宁
9.5_PULSE_WIDTH Downloaded：0: based on Verilog-HDL hardware Circuit of 9.5 pulse cycle of measurement and display 9.5.1 pulse cycle 9.5.2 cycle measurement principle, the principle 9.5.3 cycle measurement Module Design and Implementation 9.5.4 statem
Date : 2025-05-19 Size : 5kb User : 宁宁
9.6_PULSE_Level Downloaded：0: Verilog-HDL-based hardware circuits to achieve 9.6 high and low pulse duration measurement and 9.6.1 show the high and low pulse duration of the working principle of measuring the high-low 9.6.2 duration measurement modu
Date : 2025-05-19 Size : 5kb User : 宁宁
9.7_DIRIVER_control Downloaded：1: based on Verilog-HDL hardware Circuit of 9.7 Stepper Motor Control 9.7 .1 stepper motor-driven logic symbols 9.7.2 stepper motor driven map the chronology-- Step 9.7.3 Machine-driven logic diagram 9.7.4 Counting Module D
Date : 2025-05-19 Size : 2kb User : 宁宁
9.8_DISP256_GUO Downloaded：0: based on Verilog-HDL hardware Circuit of 9.8 based on the lattice of 256 Chinese character display 9.8.1 static single Chinese character display and the design principle Simulation 9.8.2 single Chinese character was geos
Date : 2025-05-19 Size : 1kb User : 宁宁
VHDLexample49 Downloaded：0: VHDL 49 examples, examples of rich, counters, state machines, register, Hamming ECC encoder, Games, etc.
Date : 2025-05-19 Size : 43kb User : 刘一
I2C_altera Downloaded：0: I2C Note! FPGA-based nuclear I2C bus control design, we look at the help
Date : 2025-05-19 Size : 43kb User : 卢俊超

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