VHDL-FPGA-Verilog List Page 4174

VHDL-FPGA-Verilog list

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adder_4bit Downloaded：0: four adder with OrCAD completed, can be used for eight or even 16 Adder design prototype
Date : 2025-05-19 Size : 1kb User : z9z9
SCAN4 Downloaded：0: four signal detector, complete with OrCAD for the input signal and the signal for more monitoring
Date : 2025-05-19 Size : 1kb User : z9z9
conter1 Downloaded：0: a VHDL counter. Can be further converted into actual use of the Counter
Date : 2025-05-19 Size : 1kb User : z9z9
COUNT100 Downloaded：0: a digital counter, every 100 seconds is a pulse output signal can be used for timing control
Date : 2025-05-19 Size : 1kb User : z9z9
SHIFTLNE Downloaded：0: VHDL under the Digital shifter and can be used for rapid multiplication using two 229 hope you like
Date : 2025-05-19 Size : 1kb User : z9z9
I60BCD Downloaded：0: I60BCD is a digital clock display module, you can also modified it into other equipment Display
Date : 2025-05-19 Size : 1kb User : z9z9
AEScoremodules Downloaded：0: AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Date : 2025-05-19 Size : 10kb User : 许茹芸
rs_decoder_31_19_6.tar Downloaded：1: Hard-decision decoding scheme Codeword l KV (n) : 31 symbols. Message length (k) : 19 symbols. Error correction capability (t) : 6 symbols One symbol represents five bit. Uses GF (2 ^ 5) with primitive polynomial p (x) =
Date : 2025-05-19 Size : 14kb User : 许茹芸
duogongnengdianzizhong Downloaded：0: with whole point timekeeping function, the whole point ringing 5s. Have control startup and shutdown functions. Get up with adjustments bell, lights-out bell time function. Bell has adjusted duration and the duration of
Date : 2025-05-19 Size : 919kb User : 吴声炬
vgactrl Downloaded：0: vga control circuit original code. Sequencers have a major modules of exotic produce modules and interface modules. Procedures in the main state machine to achieve, two counter to the state control and overturned.
Date : 2025-05-19 Size : 1kb User : lili
xapp935 Downloaded：0: ddr2 controller, verilog source code from xilinx
Date : 2025-05-19 Size : 339kb User : Hubert
656to601 Downloaded：0: the program CCIR656 video image conversion CCIR601 format, The environment is the use of Quartus II 4.0
Date : 2025-05-19 Size : 551kb User : 吉克

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