CodeBus
www.codebus.net
Search
Sign in
Sign up
Hot Search :
Source
embeded
web
remote control
p2p
game
More...
Location :
Home
SourceCode
Embeded-SCM Develop
VHDL-FPGA-Verilog
Main Category
SourceCode
Web Code
Develop Tools
Document
Other resource
Search in result
Search
VHDL-FPGA-Verilog list
Sort by :
«
1
2
...
.26
.27
.28
.29
.30
3931
.32
.33
.34
.35
.36
...
4310
»
quant
Downloaded:0
Quantitative algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Date
: 2025-06-08
Size
: 14kb
User
:
caesar
iquant
Downloaded:0
FPGA used to quantify anti-HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Date
: 2025-06-08
Size
: 13kb
User
:
caesar
rle
Downloaded:0
Variable-length encoding for FPGA HDL coding algorithms, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Date
: 2025-06-08
Size
: 4kb
User
:
caesar
zigzag
Downloaded:0
脫脙脫脷FPGA渭脛Z 卤 盲 禄炉 脣茫 篓 渭脛HDL 卤 脿脗毛 拢 卢 掳 眉脌 篓 VHDL 录 掳 Verilog
Date
: 2025-06-08
Size
: 7kb
User
:
caesar
zigzag_decode
Downloaded:0
FPGA for the anti-Z transform algorithm of Verilog code. Can be used in JPEG and MPEG compression algorithms.
Date
: 2025-06-08
Size
: 3kb
User
:
caesar
main
Downloaded:0
altera de2 sd card source. Debugging succe
Date
: 2025-06-08
Size
: 1kb
User
:
娟娟
dds
Downloaded:0
FPGA realization of the use of DDS, sine wave output, output frequency adjustable
Date
: 2025-06-08
Size
: 458kb
User
:
qlg
key
Downloaded:0
FPGA-based programmable logic device stand-alone keyboard design, the internal hardware to jitter circuit. Worth a visit
Date
: 2025-06-08
Size
: 165kb
User
:
qlg
peizhi
Downloaded:0
altera in detail the use of manual configuration, has a certain reference value, a more detailed written
Date
: 2025-06-08
Size
: 3.46mb
User
:
qlg
sin
Downloaded:0
The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
Date
: 2025-06-08
Size
: 618kb
User
:
qlg
Viterbi_RAKE
Downloaded:0
This is a description language with verilog viterbi decoding and rake receiver of the article, very practical, here are grateful for this article was
Date
: 2025-06-08
Size
: 8.43mb
User
:
骆军
1253
Downloaded:0
Based on the VHDL language and string conversion process, there are four parallel output is converted to serial output
Date
: 2025-06-08
Size
: 3kb
User
:
Hargie
«
1
2
...
.26
.27
.28
.29
.30
3931
.32
.33
.34
.35
.36
...
4310
»
CodeBus
is one of the largest source code repositories on the Internet!
Contact us :
1999-2046
CodeBus
All Rights Reserved.