VHDL-FPGA-Verilog List Page 3930

VHDL-FPGA-Verilog list

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3 Downloaded：0: Based on the VHDL language for selecting the three sequences, you can have a cycle for cycle 7 m sequence
Date : 2025-06-08 Size : 3kb User : Hargie
1 Downloaded：0: Based on the VHDL language decoding Hamming Code, which contains sub-calibration error with error correction function
Date : 2025-06-08 Size : 3kb User : Hargie
5 Downloaded：0: String and the conversion process, from the serial output is converted to 4-bit parallel output
Date : 2025-06-08 Size : 3kb User : Hargie
VGA_STUDY--OK Downloaded：0: VGA test procedure can be displayed color stripes, using VHDL language, tested and stable operation with Notes!
Date : 2025-06-08 Size : 319kb User : 于来宝
7led Downloaded：0: dp_xiliux the CPLD Verilog design experiments, 7 LED demo. code test.
Date : 2025-06-08 Size : 89kb User : pp
clock Downloaded：0: dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
Date : 2025-06-08 Size : 78kb User : pp
ledwater Downloaded：0: dp_xiliux the CPLD Verilog design experiments, water lamp demonstration. code test.
Date : 2025-06-08 Size : 41kb User : pp
rs232 Downloaded：0: dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
Date : 2025-06-08 Size : 119kb User : pp
wordfile Downloaded：0: This document is formatted UltraEdit document describes some of the original UltraEdit as a result of HDL does not support formatting language shows that the document received decompression wordfile.txt replace its insta
Date : 2025-06-08 Size : 31kb User : 钟毓秀
rs232_vhd Downloaded：0: RS232 communication protocol with the VHDL language, based on the Altium Designer
Date : 2025-06-08 Size : 2.72mb User : yato_logo
B_to_D Downloaded：0: VHDL language with the binary data into decimal data and decimal places separated from each store individually. Realize the use of state machine, the program is simple, simulation results are satisfactory, occupation of
Date : 2025-06-08 Size : 1kb User : yato_logo
LPM_ROMsin_signal_generator(12×256)MAX502 Downloaded：0: Based on 12 of the MAX502 chip DAC chips in parallel procedures, the use of FPGA in the ROM look-up table for data storage
Date : 2025-06-08 Size : 255kb User : 刘杰

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