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VHDL-FPGA-Verilog list
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Using Verilog languages realize NAND Flash block to control access as well as the synchronization FIFO control
Date : 2025-06-08 Size : 6kb User : 刘义春

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ALTERA the DE2 platform VGA interface applications, from top to bottom KEY0-KEY3 about control, so that the screen cursor by the Verilog description.
Date : 2025-06-08 Size : 761kb User : 徐朝凯

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Using ALTERA on DE2 platform, use the Verilog description of the traffic light control.
Date : 2025-06-08 Size : 257kb User : 徐朝凯

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ALTERA on DE2 platform, using internal 50M Hz clock, in the digital control simulation show time (hours minutes and seconds).
Date : 2025-06-08 Size : 595kb User : 徐朝凯

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Using VHDL realize CPLD (EMP240T100C5) of the PWM output
Date : 2025-06-08 Size : 170kb User : ZXQ

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Using VHDL realize CPLD (EPM240T100C5) output of the VGA screen
Date : 2025-06-08 Size : 225kb User : ZXQ

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Using VHDL realize CPLD (EPM240T100C5) the serial receive procedure
Date : 2025-06-08 Size : 197kb User : ZXQ

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Using VHDL realize CPLD (EPM240T100C5) Serial sending procedures
Date : 2025-06-08 Size : 189kb User : ZXQ

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Realize a 4-story single-elevator control system. Door can automatically switch can also manually switch. Code can be integrated, no more than drive the phenomenon.
Date : 2025-06-08 Size : 3kb User : 幻婳

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In VHDL on the preparation of a UART communication protocol, for FPGA development of great help
Date : 2025-06-08 Size : 140kb User : 王忠

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Discrete cosine transform and inverse discrete cosine transform of the HDL code and test files. Including VHDL and Verilog versions. And MEPG can use JPEG compression algorithm.
Date : 2025-06-08 Size : 29kb User : caesar

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The huffman algorithm for FPGA HDL coding, including VHDL and Verilog code. Can be used in JPEG and MPEG compression algorithms.
Date : 2025-06-08 Size : 10kb User : caesar
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