VHDL-FPGA-Verilog List Page 3892

VHDL-FPGA-Verilog list

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usb_xilinx_vhdl Downloaded：0: UWB realize the VHDL language, rare earth ah
Date : 2025-08-24 Size : 55kb User : yangwei
Chapter Downloaded：0: Xilinx FPGA to achieve the company
Date : 2025-08-24 Size : 10kb User : 张浩
ref-sdr-sdram-verilog Downloaded：0: SDRAM
Date : 2025-08-24 Size : 701kb User : 吴厚航
counter Downloaded：0: Verilog written procedures for counting frequency meter module,
Date : 2025-08-24 Size : 142kb User : chen
dispdecoder Downloaded：0: written in Verilog Digital Cymometer display module can be
Date : 2025-08-24 Size : 109kb User : chen
gate_control Downloaded：0: written in Verilog digital frequency meter control module, the program control
Date : 2025-08-24 Size : 95kb User : chen
dispselect Downloaded：0: written in Verilog digital frequency meter option module, used and display options
Date : 2025-08-24 Size : 81kb User : chen
CHWCNTACORA Downloaded：0: VHDL programming language design, indicator lights, indicating the word VHDL.
Date : 2025-08-24 Size : 8kb User : 张永强
hdl Downloaded：0: This is written in Verilog HDL with adjustable duty cycle frequency controller, can be hung on the Avalon bus use
Date : 2025-08-24 Size : 5kb User : 阿明
DE2Project_restored Downloaded：0: A complete design DE2_project, everyone would like to be helpful, thank you ok
Date : 2025-08-24 Size : 18.79mb User : jiayue
dds Downloaded：0: Based on VHDL+ FPGA design of the DDS signal has been through mode
Date : 2025-08-24 Size : 547kb User : 陈阳
EX Downloaded：0: Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized
Date : 2025-08-24 Size : 4kb User : hugo

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