VHDL-FPGA-Verilog List Page 3888

VHDL-FPGA-Verilog list

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HCIUART Downloaded：0: Bluetooth HCI-UART and parallel port control interface of the FPGA design
Date : 2025-06-10 Size : 100kb User : 陈臣
ch1 Downloaded：0: cpld/fpga outlined as well as the hardware description language design some of the concepts
Date : 2025-06-10 Size : 190kb User :
Key-200893142940130 Downloaded：0: Subway ticket on some of the features of the VHDL-based auto-buying classic design procedure
Date : 2025-06-10 Size : 99kb User : 小震
usb_jtag Downloaded：0: FPGA, CPLD chip usb data download lines, download speed is the parallel port of the five, with a schematic diagram of procedures in
Date : 2025-06-10 Size : 229kb User : 李聚光
music Downloaded：0: Bleeding FPGA, using VHDL to do a music box, please instruct heroes.
Date : 2025-06-10 Size : 298kb User : tianxingjianma
I2C Downloaded：0: I2C the VHDL source code, from the mode, the compiler through.
Date : 2025-06-10 Size : 2kb User : hou dong
FIFO Downloaded：0: The realization of asynchronous FIFO can be comprehensive, verifiable] keywords: almost_full, full, almost_empty, empty
Date : 2025-06-10 Size : 1kb User : ly
x_hdl Downloaded：0: VHDL2verilog procedures, I believe very helpful to everyone
Date : 2025-06-10 Size : 3.84mb User : navy
an_jian_qu_dou_dong Downloaded：0: Button can be used to jitter circuit applications, the preparation of the use of VHDL
Date : 2025-06-10 Size : 164kb User : xjl
alarm_system Downloaded：0: Electronic alarm: FPGA-based electronic alarm clock design, modular approach
Date : 2025-06-10 Size : 2.1mb User : xjl
password_lock Downloaded：0: Electronic code locks, FPGA-based design, can be set 6 password
Date : 2025-06-10 Size : 1.36mb User : xjl
texi_jifei_system Downloaded：0: FPGA-based billing system of a taxi, using top-down design methodology
Date : 2025-06-10 Size : 637kb User : xjl

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