VHDL-FPGA-Verilog List Page 3889

VHDL-FPGA-Verilog list

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MinWinsockSpi Downloaded：0: verilog ADPLL file with testbench
Date : 2025-06-10 Size : 193kb User : xgh
SPI_FireWall Downloaded：0: verilog spi file with testbench
Date : 2025-06-10 Size : 2.8mb User : xgh
VCchuankou Downloaded：1: verilog ADPLL file with testbench
Date : 2025-06-10 Size : 202kb User : xgh
top_2 Downloaded：0: Based on the attendance CPLD design, a few team names with three-dimensional storage
Date : 2025-06-10 Size : 5.26mb User : lijin
`5_TrafficLight Downloaded：0: Two-way traffic lights at the crossroads of the VHDL source code control, graduation design,
Date : 2025-06-10 Size : 75kb User : wang
SPIBusVerilog Downloaded：0: SPI serial bus interface Verilog realization elaborate on the realization of the process.
Date : 2025-06-10 Size : 389kb User : zhlm88
LDPC_Behavioral_VHDL Downloaded：0: Using VHDL language LDPC code hardware implementation language, compared to Verilog, and relatively simple
Date : 2025-06-10 Size : 2kb User : 王明
checkNodee_Behavioral_VHDL Downloaded：0: LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language
Date : 2025-06-10 Size : 1kb User : 王明
bitNode_Behaviora_VHDL Downloaded：0: LDPC code of the message node (Bitnode) news update process of the VHDL language
Date : 2025-06-10 Size : 1kb User : 王明
adder Downloaded：0: cpld/fpga common adder Verilog design procedures
Date : 2025-06-10 Size : 2kb User : 陈臣
RSdecoder Downloaded：0: cpld/fpga RS (204,188) decoder of the Verilog program
Date : 2025-06-10 Size : 13kb User : 陈臣
CIC Downloaded：0: cpld/fpga Integral comb filter (CIC) design
Date : 2025-06-10 Size : 1kb User : 陈臣

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