VHDL-FPGA-Verilog List Page 3891

VHDL-FPGA-Verilog list

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1_LAB Downloaded：0: Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized
Date : 2025-08-24 Size : 5.84mb User : hugo
MiniStep Downloaded：0: XC95144 stepper motor drive source, using verilog vhdl development, personal originality
Date : 2025-08-24 Size : 4.63mb User : 王明新
bintoBCD Downloaded：0: Introduction based on Altera
Date : 2025-08-24 Size : 226kb User : 焦扬
8259 Downloaded：0: 8259 interrupt controller, online reference source, but he had transferred Qualcomm, and applications in the control card and communication card.
Date : 2025-08-24 Size : 179kb User : 高超
VERILOGHDL Downloaded：0: this a book about the verilog-hdl design and circuit simulation and synthesize example
Date : 2025-08-24 Size : 140kb User : 管清宇
a8254 Downloaded：0: I have written 8254 counter/timer, realize all the six kinds of patterns, and the U.S. share.
Date : 2025-08-24 Size : 4.66mb User : 高超
VerilogHDL Downloaded：0: verilog hdl Comprehensive practical tutorial, a very useful book to learn to understand
Date : 2025-08-24 Size : 2.41mb User : 管清宇
verilogHDL.tar Downloaded：0: VerilogHDL courseware, teachers are now using this class
Date : 2025-08-24 Size : 1.4mb User : luolaoda
Viterbi_IP Downloaded：0: viterbi decoder IP core, the compiler can directly use
Date : 2025-08-24 Size : 74kb User : nianln
528995200441123245276683 Downloaded：0: FPGA-based multi-functional electronic clock design to use would like to help everyone ah
Date : 2025-08-24 Size : 340kb User : xhb
899207KEYBOARD_DEC-vhdl Downloaded：0: The design of digital self-Ping Wong Wing-show as early as practical design Dafang ijasd
Date : 2025-08-24 Size : 1kb User : xhb
MFSK Downloaded：0: Multi-band digital frequency modulation (MFSK) system VHDL procedures
Date : 2025-08-24 Size : 1kb User : hong

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