VHDL-FPGA-Verilog List Page 345

VHDL-FPGA-Verilog list

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Intro-VHDL-3-part2 Downloaded：0: intro VHDL part 3 section 1, electronic enginering
Date : 2025-08-23 Size : 272kb User : Volta
Manual-VHDL Downloaded：0: Manuel VHDL, electronic enginering
Date : 2025-08-23 Size : 1.04mb User : Volta
counter8 Downloaded：0: Using vhdl language and platform quartus established 8-bit counter simple simulation
Date : 2025-08-23 Size : 2.75mb User : 高成
fdivision Downloaded：0: In quartus platform and use verillog hdl write clock divider simulation
Date : 2025-08-23 Size : 2.85mb User : 高成
lcd-1602 Downloaded：0: On the use of the 4-port lcd1602 display, usually by 8-port display the uploaded this is ise in the established engineering
Date : 2025-08-23 Size : 32kb User : 陈建祥
N-jifenpin Downloaded：0: With verilog written N times odd divider source code, you can refer to Ha ha ha. Great God hope corrected
Date : 2025-08-23 Size : 171kb User : 陈建祥
RS232 Downloaded：0: Verilog prepared using RS232 serial communication source code, we can refer to Ha ha ha. Great God hope corrected
Date : 2025-08-23 Size : 491kb User : 陈建祥
mig_7series_v1_9 Downloaded：0: DDR3 Controller，complete DDR3 controll，have pass verificaion.
Date : 2025-08-23 Size : 33.97mb User : 李
pcie_7x_v1_9 Downloaded：0: PCIT Controller ，Which speed up to 5G per lane
Date : 2025-08-23 Size : 603kb User : 李
uart_rx Downloaded：0: UART receive module，complete all Baud rate transfer receive。
Date : 2025-08-23 Size : 1kb User : 李
uart_tx Downloaded：0: UART transmit module，contain start bit，data bit，check bit. have passed verification
Date : 2025-08-23 Size : 1kb User : 李
floatadd Downloaded：0: 32-bit floating-point addition, the use of language is verilog. Including is v of the engineering documents.
Date : 2025-08-23 Size : 2kb User : 小王

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