VHDL-FPGA-Verilog List Page 347

VHDL-FPGA-Verilog list

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Camera_ED Downloaded：0: Camera interface program, collecting data the camera HDMI interface displayed on the LCD screen above
Date : 2025-06-09 Size : 191kb User : wangruiqi
sd_ctrl Downloaded：0: Verlog implementation of the SD card control procedures, has been compiled under the quartus validation
Date : 2025-06-09 Size : 5kb User : 蒋磊
vga Downloaded：0: Link the VGA adapter located in the altera DE2board to a monitor
Date : 2025-06-09 Size : 695kb User : nisal senarathne
spi_module Downloaded：0: FPGA and SPI
Date : 2025-06-09 Size : 1kb User : gxb
i2c_latest.tar Downloaded：0: Synthesizable iic slave module.Modelsim simulation passed.
Date : 2025-06-09 Size : 1.41mb User : yxd
mariobros Downloaded：0: simula la musica de mario bros por medio de sonidos mediante una fpga
Date : 2025-06-09 Size : 994kb User : jesssk
MAX197-5STATE Downloaded：0: Use Verilog in Quartus II prepared MAX197 AD collection procedures, the system clock 50MHz. Tested fully use.
Date : 2025-06-09 Size : 10.35mb User : carlosdon
DA_TLC5620 Downloaded：0: Verilog TLV5620 program to achieve multi-channel DA module control, waveform signal output.
Date : 2025-06-09 Size : 4.82mb User : 张工
AD_TLC549CP Downloaded：0: Control TLC549 chip AD conversion, the corresponding analog into digital quantity, and digital quantity through the digital tube display.
Date : 2025-06-09 Size : 5.18mb User : 张工
beep Downloaded：0: Based quartusii design fpga buzzer experiments, testing the buzzer is working,
Date : 2025-06-09 Size : 2.94mb User : 杨吉
Lab01 Downloaded：0: verilog Getting exercises, including full Verilog examples, including all documents simulation, mainly on the register definition, name mapping, RS trigger definition, etc.
Date : 2025-06-09 Size : 12kb User : gaobo
Part3 Downloaded：0: This program is developed for altera DE2 board. It consist of a real time clock with time set and reset.
Date : 2025-06-09 Size : 842kb User : nisal senarathne

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