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VHDL-FPGA-Verilog list
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SATA_IP_FPGA
Downloaded:0
SATA1.0 IP based on Fpga
Date
: 2025-06-08
Size
: 4.06mb
User
:
wang
SATA_Procotol_Summary
Downloaded:0
SATA Technology
Date
: 2025-06-08
Size
: 5.51mb
User
:
wang
SATA3.0
Downloaded:0
SATA3.0 Procotol
Date
: 2025-06-08
Size
: 7.59mb
User
:
wang
svpwm
Downloaded:0
Permanent magnet synchronous motor SVPWM, motor PWM wave generation program,
Date
: 2025-06-08
Size
: 214kb
User
:
daiming
mux16
Downloaded:0
The program is to take advantage of the sequential logic design method to design a 16-bit multiplier
Date
: 2025-06-08
Size
: 425kb
User
:
穆毅蚺
keyscanverilog
Downloaded:0
In the button is pressed or released When there will be an unstable time jitter, jitter if you do not handle this time, we can not deal with the key Coding, so our design must effectively eliminate key jitter.
Date
: 2025-06-08
Size
: 299kb
User
:
穆毅蚺
vivado2016.2-license
Downloaded:0
the license of Vivado Design Suite v2016.2
Date
: 2025-06-08
Size
: 1kb
User
:
ranbowang
anjian
Downloaded:0
Key acne procedures, very easy to use, we can try
Date
: 2025-06-08
Size
: 1kb
User
:
陈建祥
13_flash_test
Downloaded:0
SPI Flash driver program,use Verilog HDL,successfully tested.
Date
: 2025-06-08
Size
: 9.59mb
User
:
zhanghc
15_usb_test
Downloaded:0
USB driver program with VerilogHDL,successful tested.
Date
: 2025-06-08
Size
: 3.12mb
User
:
zhanghc
Verilog-IIC-read-MPU6050-Filter
Downloaded:0
Verilog codes read 6 axis data of MPU6050, and use GY AZ AX with complementary filtering arithmetic to calculate X axis angle. Codes run at Altera Chip EP4C15F17C8 and set 2 led light if X angle beyond ±5°. Zip includes
Date
: 2025-06-08
Size
: 9.06mb
User
:
魏溢
jiaotongdeng-FPGA
Downloaded:0
Traffic light controller controls the two main roads traffic intersection, crossing vehicles, straight signal, left turn signal shown separately, the transit time a, b is equal to two main roads, which indicates straight
Date
: 2025-06-08
Size
: 2.1mb
User
:
江楠
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.36
.37
.38
.39
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341
.42
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.45
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4310
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