VHDL-FPGA-Verilog List Page 336

VHDL-FPGA-Verilog list

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timer16 Downloaded：0: realizaiton of timer16
Date : 2025-08-22 Size : 36kb User : 朴巍
uart_rx Downloaded：0: Serial receive module code, according to the set baud rate, serial data can be correctly received
Date : 2025-08-22 Size : 1kb User : Kevin
practica1 Downloaded：0: tester.vhd library IEEE use IEEE.STD_LOGIC_1164.all use IEEE.STD_LOGIC_ARITH.all use IEEE.STD_LOGIC_UNSIGNED.all LIBRARY lpm USE lpm.lpm_components.ALL entity practica1 is port ( RESET : in std_logic clk : in std_logic
Date : 2025-08-22 Size : 1kb User : pablo
spartan_mig20 Downloaded：0: programer for FPGA with spatan
Date : 2025-08-22 Size : 10kb User : hiep
fft1024 Downloaded：1: 1024 point fft FPGA hardware implementation
Date : 2025-08-22 Size : 55.9mb User : 陈峰
VGA_pic_200x200x3(ok) Downloaded：0: Altera series FPGA to achieve the VGA display 8 color images, debugging through, the development environment QuartusII, language verilog.
Date : 2025-08-22 Size : 6.56mb User : PrudentMe
DDS(ok) Downloaded：0: Make ROM sine table and fill the ROM internal FPGA, by calling the internal data to achieve the sine wave output, development environment QuartusII, Language Verilog, debugging through, with Modelsim debugging results.
Date : 2025-08-22 Size : 9.68mb User : PrudentMe
PCIe Downloaded：0: Use Altera PCIe IP core, supplement PCIe transaction layer, complete PCIe device side hardware design
Date : 2025-08-22 Size : 27.64mb User : zhaodonglin
DES-Verilog-master Downloaded：0: DES encrypt verilog
Date : 2025-08-22 Size : 11kb User : lv
apbtoaes128_latest.tar Downloaded：0: AES encryption algorithm verilog code, based on the APB bus interface digital IP, contains a detailed testbench
Date : 2025-08-22 Size : 195kb User : lv
apbi2c_latest.tar Downloaded：0: APB bus interface to I2C bus interface IP，verilog code
Date : 2025-08-22 Size : 434kb User : lv
lcd Downloaded：0: Using Xilinx' s Virtex-5 chip lcd procedure
Date : 2025-08-22 Size : 300kb User : zsd

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