VHDL-FPGA-Verilog List Page 332

VHDL-FPGA-Verilog list

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module-car Downloaded：0: this program describes the state machine function by verilog code
Date : 2025-06-08 Size : 11kb User : Sureetha
ARM-LED Downloaded：0: this code gives the function of ARM processor
Date : 2025-06-08 Size : 10kb User : Sureetha
ARM7SEG Downloaded：0: this code gives the ARM processor function in 7segment
Date : 2025-06-08 Size : 10kb User : Sureetha
Proteus-lcd Downloaded：0: This gives the function of proteus
Date : 2025-06-08 Size : 11kb User : Sureetha
State-Machine Downloaded：0: This gives the function of state machine
Date : 2025-06-08 Size : 11kb User : Sureetha
scsa Downloaded：0: Speculative variable latency adders have attracted strong interest thanks to their capability to reduce average delay compared to traditional architectures. This proposes a novel variable latency speculative adder based
Date : 2025-06-08 Size : 2kb User : preethi/charu
Han-carlson.ppt Downloaded：0: Abstract—Variable latency adders have been recently proposed in literature. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the co
Date : 2025-06-08 Size : 42kb User : preethi/charu
mux Downloaded：0: This file is about mux in ISE by VHDL language.
Date : 2025-06-08 Size : 9kb User : najme
shizhong Downloaded：0: VHDL design with alarm 59 minutes timer
Date : 2025-06-08 Size : 14kb User : 王一
ALU-Design Downloaded：0: 8 bit alu design features: optimized design inclusive of multiplier
Date : 2025-06-08 Size : 1019kb User : Ashutosh
float_point_divide.tar Downloaded：0: this project divide two floating point number.
Date : 2025-06-08 Size : 182kb User : ali
VHDL_4bit_magnde_compar_code_dataflow Downloaded：0: this is a source code for a 4 bit magnitude comparator using dataflow technique a 4 bit magnitude comparator logic circuit.
Date : 2025-06-08 Size : 1kb User : KENNETH JAJA

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