VHDL-FPGA-Verilog List Page 335

VHDL-FPGA-Verilog list

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UART-master Downloaded：0: UART interface verilog code, uart_tx、uart_rx， testbench
Date : 2025-06-08 Size : 192kb User : lv
gpio-master Downloaded：0: WISHBONE interface to GPIO verilog code, GPIO define, RTL sim, syn
Date : 2025-06-08 Size : 410kb User : lv
FSMpart2 Downloaded：0: Verilog implementarion of FSM. Solution for altera s lab 7 part2.
Date : 2025-06-08 Size : 10kb User : iago
part3FSM Downloaded：0: Verilog FSM implementation for altera s lab(part 3 of lab 7).
Date : 2025-06-08 Size : 8kb User : iago
FSMpart4 Downloaded：0: Verilog FSM implemetation for altera s lab 7(part IV) for de2115 fpga.
Date : 2025-06-08 Size : 9kb User : iago
FSMpart5 Downloaded：0: FSM Verilog implementation of the final part of lab 7 of altera s verilog tutorial for de2115 fpga.
Date : 2025-06-08 Size : 9kb User : iago
sos_module Downloaded：0: Realized by FPGA sos mole password, the output signal level of short duration. There is a sequence of output control points Moss password, painting and intervals. And control_module.v is a simple timer triggers, each per
Date : 2025-06-08 Size : 7.97mb User : 洪伟达
TECOM Downloaded：0: fpga pmsm te
Date : 2025-06-08 Size : 28kb User : 申彦磊
7-segment-counter Downloaded：0: 7 segment counter in VHdl
Date : 2025-06-08 Size : 2.22mb User : yassine
crc16_d8 Downloaded：0: This code USES the Verilog language function of eight CRC check the CRC- ITU CRC16 calibration standards
Date : 2025-06-08 Size : 1kb User : zhangpeng
colorchecker Downloaded：0: colorchecker VGA format standard color card production, can support any resolution settings
Date : 2025-06-08 Size : 1kb User : 周召涛
gtx_interface_ip Downloaded：0: High-speed serial design FPGA-GTX IP settings generated dynamically configurable rate of 2.4Gbps, 1.2Gbps, 0.6Gbps, adaptive link
Date : 2025-06-08 Size : 1.14mb User : 周召涛

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