VHDL-FPGA-Verilog List Page 317

VHDL-FPGA-Verilog list

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register Downloaded：0: Using Verilog to achieve a basic register, and led lights and simulation to show the read and write data.
Date : 2025-06-07 Size : 1kb User : east
code_lagrange_interpolation Downloaded：0: Use verilog to achieve Lagrange interpolation, very useful value, there is a need to refer to
Date : 2025-06-07 Size : 8kb User : 华天
1602verilog Downloaded：0: Using Verilog language to complete the 1602 LCD screen driver display
Date : 2025-06-07 Size : 6.72mb User : shangying
Frequce Downloaded：0: 能测量频率，并且能测占空比10 90 ，还能产生1M 占空比10 的脉冲波 Can measure the frequency, and can measure the duty cycle 10 90 , but also can produce the 1M duty cycle 10 of the pulse wave
Date : 2025-06-07 Size : 3.54mb User : Moeiy
ExperimentoCap9 Downloaded：0: Question cpa 9 of the an book in portuguese
Date : 2025-06-07 Size : 17kb User : Thiago Amaral
VGAController Downloaded：0: Easy VGAController in vhdl
Date : 2025-06-07 Size : 10.22mb User : Thiago Amaral
8a Downloaded：0: 2 Flip Flops in VHDL
Date : 2025-06-07 Size : 1kb User : Thiago Amaral
soma_loka Downloaded：0: Sum make in vhdl code
Date : 2025-06-07 Size : 1kb User : Thiago Amaral
rs_232 Downloaded：0: Comunication rs232 in vhdl
Date : 2025-06-07 Size : 1kb User : Thiago Amaral
equalizer Downloaded：0: This the code for the channel equalizer and the test bench for this in the verilog code.
Date : 2025-06-07 Size : 1kb User : rion
convolution Downloaded：0: This the code for the convolutional and the test bench for this in the verilog code.
Date : 2025-06-07 Size : 1kb User : rion
demapperSharp1(16QAM) Downloaded：0: This the code for the demapper in the verilog code.
Date : 2025-06-07 Size : 1kb User : rion

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