VHDL-FPGA-Verilog List Page 322

VHDL-FPGA-Verilog list

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MPPT_VHDL Downloaded：0: MPPT VHDL source code for photovoltaic application
Date : 2025-06-08 Size : 2.82mb User : mohamed
triangular-_VHDL Downloaded：0: VHDL source code exemple to generate triangular waveform
Date : 2025-06-08 Size : 146kb User : mohamed
svpwm Downloaded：0: SVPWM verilog source code
Date : 2025-06-08 Size : 13.66mb User : mohamed
N-BitComparator Downloaded：0: N-Bit Comparator Between X and Y
Date : 2025-06-08 Size : 667kb User : tattam
Traffic-Light-Controller Downloaded：0: Traffic Lights controller in 5 state
Date : 2025-06-08 Size : 1.15mb User : tattam
fifo_sync Downloaded：0: A Synchronous FIFO Design
Date : 2025-06-08 Size : 1kb User : Debasis
AD7606URAT Downloaded：0: AD7606 .V FPGA du chegnxu
Date : 2025-06-08 Size : 1.54mb User : 刘莹
lan91c111 Downloaded：0: MAC chip LAN91C111 driver source code, quartus development environment, Verilog HDL development language. Write debugging through their own. Very useful for FPGA control MAC developers.
Date : 2025-06-08 Size : 36kb User : gsw
15_IP_core Downloaded：0: ata, 3des vgs and other ip core. ECE395 GPU:
Date : 2025-06-08 Size : 2.33mb User : Tommy
colorbar Downloaded：0: VGA color display type vertical strip 10 parts, scan clock by instantiating the IP core PLL_CLK performed on 800* 600 resolution screen frequency to be 40MHz
Date : 2025-06-08 Size : 1.45mb User : 文锋
UART_echo Downloaded：0: It s a UART module with baud rate of 125000.
Date : 2025-06-08 Size : 9kb User : Zeze Luiz
shuzizhongchengxu Downloaded：0: 多功能数字钟，1、采用24小时制：时、分、秒计时、显示。 2、具有手动校准功能：分为时校准、分校准。 3、秒复位 4、闹钟功能 5、整点报时：仿中央人民广播电台整点报时信号
Date : 2025-06-08 Size : 6kb User : 郭丹

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