VHDL-FPGA-Verilog List Page 321

VHDL-FPGA-Verilog list

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pingppangqiuyouxiji Downloaded：0: 1, design a by A, B both sides of the competition, there are three referees table tennis game. 2, with 8 (or more) LED lined up in a straight line to the midpoint of the border, on both sides of the position on behalf of
Date : 2025-06-08 Size : 6kb User : 郭丹
mul_addtree Downloaded：0: Addition tree multiplier of 8bits
Date : 2025-06-08 Size : 1kb User : luyong
class10_HEX8 Downloaded：0: Mainly use Verilog code programming control of eight digital tube display
Date : 2025-06-08 Size : 7.48mb User : 李改有
class19_IR_code Downloaded：0: Mainly use Verilog code to decode the infrared
Date : 2025-06-08 Size : 514kb User : 李改有
class11_uart_rx Downloaded：0: Mainly use Verilog code programming serial port to receive
Date : 2025-06-08 Size : 3.6mb User : 李改有
class11_uart_tx Downloaded：0: Mainly use Verilog code programming serial port to send the program
Date : 2025-06-08 Size : 3.52mb User : 李改有
class_fifo Downloaded：0: The FPGA internal fifo calls, use Verilog programming on it
Date : 2025-06-08 Size : 10.65mb User : 李改有
des Downloaded：0: verilog DES encrypt
Date : 2025-06-08 Size : 3kb User : 翟江涛
seg_example Downloaded：1: DE2-115 seg example source code
Date : 2025-06-08 Size : 1kb User : jdj
edge_detector_logic Downloaded：0: verilog code for edge detection logic
Date : 2025-06-08 Size : 1kb User : Sai Sarvani Nainala
intra4x4 Downloaded：0: Intra4x4 in VHDL for H.264 encoder. this module work with 3 intra prediction mode
Date : 2025-06-08 Size : 1.79mb User : Roohi
UART Downloaded：0: UART (serial) protocol in VHDL with receive & send
Date : 2025-06-08 Size : 2kb User : Roohi

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