VHDL-FPGA-Verilog List Page 315

VHDL-FPGA-Verilog list

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PS2_ctrl Downloaded：0: (1) the input clock frequency division, get 190Hz and 25Hz clock signal, provided to other modules as the time Clock input (2) keyboard scan module: receive the keyboard input PS2C and PS2D, and get the keyboard scan cod
Date : 2025-06-07 Size : 423kb User : panda
VGA_disp Downloaded：0: Clk divid module for the frequency circuit, the 50MHz system clock frequency to produce 50M/7Hz pixel clock. VGA control module for the VGA display control circuit module, driven by the pixel clock in the first line-freq
Date : 2025-06-07 Size : 1.2mb User : panda
traffic-light Downloaded：0: (1) Divid module: 1Hz divider module, the development board provides 50MHz system clock, and the design of traffic lights Conversion in seconds for the time unit, the 50MHz frequency to be 1Hz pulse signal. (2) Divid_200
Date : 2025-06-07 Size : 521kb User : panda
sin_en Downloaded：0: DDS by the phase increment, phase accumulator, quantizer and sine and cosine lookup table of four parts. The phase accumulator accumulates a fixed phase value for each period, and then finds the corresponding value the l
Date : 2025-06-07 Size : 2.59mb User : panda
clock Downloaded：0: VHDL language with the design of digital clock, in the digital display minutes and seconds, and can manually adjust the minutes, To achieve the increase or decrease minutes. The design includes the following sections: (1
Date : 2025-06-07 Size : 484kb User : panda
Fibonacci Downloaded：0: (1) clkdiv module: the 50MHz system clock frequency, were 190Hz, 3Hz signal. The 190 Hz signal is used to dynamically scan the module bit signal and the 3 Hz signal is used for the fib module. (2) fib module: According t
Date : 2025-06-07 Size : 652kb User : panda
URAT Downloaded：0: In the ISE environment, using VHDL language RS232 serial port design, serial communication. Through the serial debugging tool to 0000000UART Send a hexadecimal number, FPGA serial data received by the UART converted to p
Date : 2025-06-07 Size : 394kb User : panda
count Downloaded：0: This experiment uses VHDL hardware description language to design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger Clock, the counter counts up, and the use of digital tube display, when the c
Date : 2025-06-07 Size : 464kb User : panda
up_counter_8 Downloaded：0: Code for 8bit up counter in Verilog
Date : 2025-06-07 Size : 42kb User : zsan
Rising_edge_detect Downloaded：0: Rise edge detect code in Verilog
Date : 2025-06-07 Size : 115kb User : zsan
decoder_38 Downloaded：0: FPGA experiment, based on the VHDL language a decoder 38, actual effect is very good, please advice
Date : 2025-06-07 Size : 113kb User : 张鹏飞
dig_watch Downloaded：0: Fpga experiment, the digital stopwatch designed based on VHDL language, which contains a storage module.
Date : 2025-06-07 Size : 3.06mb User : 张鹏飞

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