VHDL-FPGA-Verilog List Page 3148

VHDL-FPGA-Verilog list

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quaddecoder_verilog_ise11.2_used_09042010 Downloaded：0: Two simple Quadrature decoder and Counter build in a XILINX XC9536 CPLD. This Core is coded in Verilog and contains the compete Project file and the fitted quad.jed File. The Pinout is descripted in the Constrained file
Date : 2025-07-31 Size : 69kb User : JUPP
digital_frequency Downloaded：0: This is a method of designing a digital frequency-measuring device. It can measure frequency ranging from 0.5Hz to 10MHz. It is developed in the program of Quartus.
Date : 2025-07-31 Size : 481kb User : 孙岩
fenpinpi Downloaded：0: quartusii software simulation code divider
Date : 2025-07-31 Size : 408kb User : 张惠
jiafaqi Downloaded：0: quartusii software simulation code decimal addition counter
Date : 2025-07-31 Size : 330kb User : 张惠
miaobiao Downloaded：0: quartusii software simulation code stopwatch 24 hour time
Date : 2025-07-31 Size : 730kb User : 张惠
8051_latest.tar Downloaded：0: VHDL/VERILOG FOR 8051 Core
Date : 2025-07-31 Size : 6.68mb User : mss
can_latest.tar Downloaded：0: VHDL/VERILOG FOR CAN BUS Core
Date : 2025-07-31 Size : 1.12mb User : mss
i2cslave_latest.tar Downloaded：0: VHDL/VERILOG FOR I2C Core
Date : 2025-07-31 Size : 1.24mb User : mss
Verilog Downloaded：0: Verilog program, prepared a taxi meter can be set according to distance pricing, valuation by waiting time. Very convenient, good interface
Date : 2025-07-31 Size : 2.07mb User : 牟星光
GPS Downloaded：0: Fpga implementation based on the gps. Code fully available
Date : 2025-07-31 Size : 12.87mb User : sky
key Downloaded：0: heguo
Date : 2025-07-31 Size : 1kb User : heguo
verilog Downloaded：0: Wen Yu Xia Beihang verilog script syntax entry ppt
Date : 2025-07-31 Size : 50kb User : 王军

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