VHDL-FPGA-Verilog List Page 3146

VHDL-FPGA-Verilog list

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paomadeng Downloaded：0: Use verilog to write marquees, has been debugged, useful
Date : 2025-07-31 Size : 307kb User : tangxiaolei
counter Downloaded：0: Written with verilog counter, can be used for frequency and other functions. Has been very good success with debugging
Date : 2025-07-31 Size : 2kb User : tangxiaolei
ddspsk Downloaded：0: 13-bit barker code, 2spk signal generation
Date : 2025-07-31 Size : 1kb User : 刘浏
lshifter Downloaded：0: Sometimes in order to process the data, you need to register in the role of data in the shift control signals, the order of low to high or to move one into the shift register
Date : 2025-07-31 Size : 1kb User : 刘浏
TLC5510 Downloaded：0: In ultrasonic flowmeter, the ad can be sampled at high speed to achieve the purpose of ad conversion
Date : 2025-07-31 Size : 5kb User : 刘浏
Xil3SD1800A_MIG Downloaded：0: The development board based on xc3sd1800afg676 DDR2 controller of IPCORE, provide a complete code and UCF. System clock frequency of 125Mhz.
Date : 2025-07-31 Size : 1.16mb User : sonicecho
mm1 Downloaded：0: Maximum and Minimum Value Selector
Date : 2025-07-31 Size : 1kb User : li yinjun
SpWIF Downloaded：0: spacewire bus transceiver interface, the source code, VHDL, applicable to Xilinx, testing FPGA: XC3S1000FTG256-4C
Date : 2025-07-31 Size : 20kb User : young
fsk_modulation Downloaded：0: Achieve FSK modulation capabilities, to change the input waveform can have different output
Date : 2025-07-31 Size : 324kb User : 纪雪莲
fsk_demodulation Downloaded：0: FSK demodulation process, and simulation graphics, change the input can have different output
Date : 2025-07-31 Size : 340kb User : 纪雪莲
uart2 Downloaded：0: a small uart implementation with Verilog
Date : 2025-07-31 Size : 1kb User : zismad
cpldtoPCvhdlcoding Downloaded：0: CPLD and VHDL code PC, communications,
Date : 2025-07-31 Size : 1kb User : 于凤萍

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