VHDL-FPGA-Verilog List Page 3153

VHDL-FPGA-Verilog list

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ExamplesofVHDLDescriptions Downloaded：0: EDA with a large number of experiments, the full text is written in English, examples using VHDL language.
Date : 2025-07-30 Size : 165kb User : sunnan
experiment Downloaded：0: 4 decimal frequency meter design, program details, can be applied directly
Date : 2025-07-30 Size : 1.73mb User : lan
QPSK Downloaded：0: QPSK
Date : 2025-07-30 Size : 41kb User : 冯晓昊
VHDLLPM Downloaded：0: Application vhdl language, called lmp block, very useful, necessary electronic design
Date : 2025-07-30 Size : 344kb User : gump
SignalTap_IIFPGA Downloaded：0: Using vhdl programming, with signaltap logical simulation, fpga, helpful
Date : 2025-07-30 Size : 214kb User : gump
A_D_translate Downloaded：0: Experimental board do ADC0809 A/D converter, test board provides analog input potentiometer, the preparation process, the analog content into binary numbers, the highest in the digital control two figures show the volume
Date : 2025-07-30 Size : 52kb User : yangxiao
display_with_dia Downloaded：0: This experimental device provides six LED display circuit 8 code, students will address output by the corresponding data can be achieved on the control display. Shows a total of 6, with the dynamically displayed. 8-bit c
Date : 2025-07-30 Size : 134kb User : yangxiao
led_control Downloaded：0: The experimental box with built-in LCD controller for the SED1520, lattice is 122 × 32, needs two SED1520 formed by the E1, E2, respectively gating to control the display of about two and a half screen. Graphic LCD modul
Date : 2025-07-30 Size : 1.15mb User : yangxiao
DDSVerilog Downloaded：0: Verilog realization of DDS source, you can use with soft-core NiosII
Date : 2025-07-30 Size : 3kb User : 张松松
yedek_son Downloaded：0: a basic Mode Decision hardware for Variable Block Size Motion Estimation in verilog
Date : 2025-07-30 Size : 2kb User : dumbmage
divider Downloaded：0: verilog divider hardware
Date : 2025-07-30 Size : 29kb User : dumbmage
GrayCounter2 Downloaded：0: gray counter for async FIFO design
Date : 2025-07-30 Size : 1kb User : zismad

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