VHDL-FPGA-Verilog List Page 3156

VHDL-FPGA-Verilog list

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DDS-FPGA Downloaded：0: FPGA-based DDS information!
Date : 2025-07-30 Size : 6.06mb User : eva
QuartusII6.0_cn Downloaded：0: QuartusII6.0 English tutorial. Pdf, said very detailed, 260 pages, very good information
Date : 2025-07-30 Size : 1.97mb User : yang
shuzizhong_vhdl Downloaded：0: Vhdl language used to write the digital clock program, interested to see
Date : 2025-07-30 Size : 3kb User : yang
jiaotongdeng Downloaded：0: Although there are many traffic lights online reference program, but Why is not very low, then Why did not the number of extensions, this is the traffic light program I wrote, absolutely super classic!
Date : 2025-07-30 Size : 24kb User : 荣少钟情
3_8CODER Downloaded：0: module decoder_38(out,in) output[7:0] out input[2:0] in reg[7:0] out always @(in)
Date : 2025-07-30 Size : 170kb User : andery
sc_camera_01APR08 Downloaded：0: FPGA-based CMOS sensor Image Transmission. The design is also based on NIOS.
Date : 2025-07-30 Size : 1.79mb User : 陈炬
USB2_chip Downloaded：0: Traffic light control is a good a program we support a ah, huh, huh.
Date : 2025-07-30 Size : 3.66mb User : jiatao
pr_hmm Downloaded：0: ~ Veterbi algorithm ~HMM~~~~~~~~~~
Date : 2025-07-30 Size : 1kb User : wjlsomeone
matrix3x3 Downloaded：0: 3* 3 matrix multiplier code~
Date : 2025-07-30 Size : 4kb User : wjlsomeone
jiaotongdeng Downloaded：0: To FPGA development platform for the traffic signal system, with a countdown and the buzzer function.
Date : 2025-07-30 Size : 1kb User : AJ
add Downloaded：0: Their own written with verilog adder, timing simulation has been adopted
Date : 2025-07-30 Size : 1kb User : 莫少宁
08-Multiplexers Downloaded：0: vhdl code for adder for quartus
Date : 2025-07-30 Size : 169kb User : jaydeep

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