VHDL-FPGA-Verilog List Page 3128

VHDL-FPGA-Verilog list

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traffic_light Downloaded：0: Implementation of traffic lights, north-south and east-west road, there is the opening of the remaining time. A simulation map
Date : 2025-08-02 Size : 188kb User : deng wensi
clock Downloaded：0: VHDL digital clock source, there are simulation plans, source code, etc.
Date : 2025-08-02 Size : 1.28mb User : deng wensi
sin_generator Downloaded：0: Sin Generator. 16 points on period.
Date : 2025-08-02 Size : 1kb User : Evgeny
reed_solomon_decoder_latest.tar Downloaded：0: reed solomon (204,188). in verilog.
Date : 2025-08-02 Size : 175kb User : Evgeny
rs_dec_enc_latest.tar Downloaded：0: Reed-Solomon (255,251). in VHDL.
Date : 2025-08-02 Size : 90kb User : Evgeny
my_reg Downloaded：0: D flip-flop, Verilog implementation, with experimental documentation.
Date : 2025-08-02 Size : 847kb User : 姚成富
my_xnor Downloaded：0: With or door, Verilog implementation, with experimental documentation.
Date : 2025-08-02 Size : 871kb User : 姚成富
my_xor Downloaded：0: XOR gate, Verilog implementation, including test documentation.
Date : 2025-08-02 Size : 873kb User : 姚成富
shift_reg Downloaded：0: Shift register, Verilog implementation, there is experimental documentation.
Date : 2025-08-02 Size : 1.23mb User : 姚成富
trafficlamp Downloaded：0: FPGA-based design of traffic lights, with red, green and yellow three-color, fully consistent with the actual, using the three process design!
Date : 2025-08-02 Size : 90kb User : qs
HDB3 Downloaded：0: Generated by FPGA digital baseband transmission code HDB3 code system, a " communication theory" example design.
Date : 2025-08-02 Size : 283kb User : qs
Quartus2(FPGACPLD) Downloaded：0: The FPGACPLD design in Quartus2 , PDF documents
Date : 2025-08-02 Size : 14.13mb User : 秋潮

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