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VHDL-FPGA-Verilog list
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QAM 16 source code for the modulation in wireless communication or broadcast. -QAM 16 source code, used in wireless communication or broadcasting.
Date : 2025-08-03 Size : 17kb User : panzhijian

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altera coedic ip core, including the document, whole design, and the testbench.
Date : 2025-08-03 Size : 875kb User : panzhijian

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NAND gate, Verilog implementation, with test documentation.
Date : 2025-08-03 Size : 877kb User :

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This is the ad904 testing procedures, using vhdl language. Whether it is normal to see it change
Date : 2025-08-03 Size : 23.18mb User : 朱西

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FPGA design of the main talk and notice some basic concepts. These are the years of FPGA design experience with a heartfelt words.
Date : 2025-08-03 Size : 944kb User : 张桂榕

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FPGA NIOSii LCD1602
Date : 2025-08-03 Size : 1kb User :

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Using TLC5510 high-speed A/D sampling. The method used to achieve a state machine, in the state st0, to A/D sampling clock adck a rising edge of, and latched A/D output
Date : 2025-08-03 Size : 172kb User : 哈哈

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Implemented on FPGA using VHDL in the 8051 core, the code is simple, easy to understand
Date : 2025-08-03 Size : 385kb User : yang fa sheng

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SHIFTER describe the functions of the shift register and the realization of VHDL hardware language
Date : 2025-08-03 Size : 3kb User : SHEIN

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THIS DESIGN IS PROVIDED TO YOU “AS IS”. XILINX MAKES AND YOU RECEIVE NO WARRANTIES OR CONDITIONS, EXPRESS, IMPLIED, STATUTORY OR OTHERWISE, AND XILINX SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, NON
Date : 2025-08-03 Size : 844kb User : qin

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Basic logic operations, Verilog implementation, with the realization of tutorials.
Date : 2025-08-03 Size : 4.85mb User :

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Verilog frequency on the sub-procedures such as the duty cycle of non-duty-cycle fractional odd frequency, etc.
Date : 2025-08-03 Size : 3kb User : 杜方
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