VHDL-FPGA-Verilog List Page 3129

VHDL-FPGA-Verilog list

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UserDefinedFunction Downloaded：0: It s a VHDL program. The program does a generic gray. Using a Cyclone II FPGA Board.
Date : 2025-08-02 Size : 237kb User : Ferdinando
speed_measure_on_7_segment Downloaded：0: Period method of frequency measuring (change constant to speed measure). DE2 Board Quartus project. Input signal on GPIO, result on 7seg, start/stop with key[0].
Date : 2025-08-02 Size : 40kb User : shaitan
comp Downloaded：0: Numerical comparator, Verilog realization of experiments with specific documentation.
Date : 2025-08-02 Size : 738kb User : mypudn0001
my_code Downloaded：0: Encoder and decoder, Verilog realization of a specific experiment documentation.
Date : 2025-08-02 Size : 1.55mb User : mypudn0001
CLanguageProgrammingForTheDevelopmentOfThoseGuidel Downloaded：0: the paper illustrates how to use software pulse width modulation (PWM), how can the design into a run in the FPGA logic blocks, and can use memory mapped I/O Interface completion of the logic block through software cont
Date : 2025-08-02 Size : 133kb User : susuwen
DSB3 Downloaded：0: Using ISE software program written in Verilog, can be bilateral with a modulation signal
Date : 2025-08-02 Size : 920kb User : 蜡笔
MyDDS Downloaded：0: Prepared using look-up table method of verilog DDS program, save the use of IP core implementation requires resources, software for the ISE,
Date : 2025-08-02 Size : 2.76mb User : 蜡笔
Walsh Downloaded：0: Prepared using ISE verilog code generated WALSH procedures, easy to understand, a little modification can generate their own like the 8,16，32，64-bit code WALSH. .
Date : 2025-08-02 Size : 173kb User : 蜡笔
Average Downloaded：0: ISE software written request using the average of the verilog program can be used to seek the average used to calculate the average amplitude of the signal
Date : 2025-08-02 Size : 189kb User : 蜡笔
Kaifang Downloaded：0: Prepared using ISE verilog program to achieve prescribing functions, using the CORDICIP nuclear, prescribing functions to be completed
Date : 2025-08-02 Size : 412kb User : 蜡笔
d-flip Downloaded：0: Synchronous reset D flip-flop, the flip-flop has a data input D, the clock input CLK, clear input CLR, the data output Q. CLR 1, the trigger reset
Date : 2025-08-02 Size : 6kb User : wangminpeng
VHDL Downloaded：0: VHDL language and application programming source code. Including the contents of Chapter 2-12. There are a practical example: the design of digital code detonator.
Date : 2025-08-02 Size : 62kb User : deng wensi

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