D flip-flop, Verilog implementation, with experimental documentation.

D触发器实验例程及文档
.....................\D触发器.pdf
.....................\my_reg
.....................\......\component
.....................\......\constraint
.....................\......\coreconsole
.....................\......\designer
.....................\......\........\impl1
.....................\......\........\.....\designer.log
.....................\......\........\.....\my_reg.adb
.....................\......\........\.....\my_reg.dtf
.....................\......\........\.....\..........\verify.log
.....................\......\........\.....\my_reg.ide_des
.....................\......\........\.....\my_reg.pdb
.....................\......\........\.....\my_reg.pdb.depends
.....................\......\........\.....\my_reg.tcl
.....................\......\........\.....\my_reg_fp
.....................\......\........\.....\.........\$$FlashPro_FPBBALTLPT1.L$$
.....................\......\........\.....\.........\my_reg.log
.....................\......\........\.....\.........\my_reg.pro
.....................\......\........\.....\.........\projectData
.....................\......\........\.....\.........\...........\my_reg.pdb
.....................\......\........\.....\simulation
.....................\......\hdl
.....................\......\...\clk_div.v
.....................\......\...\my_reg.v
.....................\......\my_reg.prj
.....................\......\phy_synthesis
.....................\......\simulation
.....................\......\..........\modelsim.ini
.....................\......\smartgen
.....................\......\........\smartgen.aws
.....................\......\stimulus
.....................\......\synthesis
.....................\......\.........\.recordref
.....................\......\.........\backup
.....................\......\.........\coreip
.....................\......\.........\my_reg.areasrr
.....................\......\.........\my_reg.edn
.....................\......\.........\my_reg.map
.....................\......\.........\my_reg.pdc
.....................\......\.........\my_reg.sdf
.....................\......\.........\my_reg.so
.....................\......\.........\my_reg.srd
.....................\......\.........\my_reg.srm
.....................\......\.........\my_reg.srr
.....................\......\.........\my_reg.srs
.....................\......\.........\my_reg.szr
.....................\......\.........\my_reg.tlg
.....................\......\.........\my_reg_sdc.sdc
.....................\......\.........\my_reg_syn.prj
.....................\......\.........\run_options.txt
.....................\......\.........\stdout.log
.....................\......\.........\syntmp
.....................\......\.........\......\my_reg.plg
.....................\......\.........\traplog.tlg
.....................\......\viewdraw
.....................\......\........\sch
.....................\......\........\sym
.....................\......\........\vf
.....................\......\........\..\project.lst
.....................\......\........\viewdraw.ini
.....................\......\........\wir

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