VHDL-FPGA-Verilog List Page 3023

VHDL-FPGA-Verilog list

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8bitRISCCPU Downloaded：0: The file is 8-bit CPU design hardware description language can be used as reference for beginners
Date : 2025-11-17 Size : 814kb User : xiaoma
Stepper_Motor_Controller_Using_LDR Downloaded：0: Controlling Speed of Stepper motor using LDR spartan 3E kit
Date : 2025-11-17 Size : 1.94mb User : Deepak Singh
FIRforVHDL Downloaded：0: 17 Order of the simple low-pass filter (FIR), with quartusII implementation (including test report)
Date : 2025-11-17 Size : 195kb User : kevinlyject
sobel Downloaded：0: Adopted verilog language realizes sobel edge detection in image processing algorithm
Date : 2025-11-17 Size : 10kb User : wkd
zidongpinlv Downloaded：0: 4 automatic transmission design a digital frequency meter, by a 4 decimal digital tube (including the decimal point) shows the results 2, the measuring range 1Hz ~ 9999KHz 3, can automatically according to seven decimal
Date : 2025-11-17 Size : 346kb User : 李伦特
VGA Downloaded：0: Based on FPGA, QUARTUSS | | development environment simple image display control
Date : 2025-11-17 Size : 602kb User : sujiebin
SPI Downloaded：0: spi IP based on fpga
Date : 2025-11-17 Size : 48kb User : wuyou
cordic_4 Downloaded：0: VHDL coding cordic
Date : 2025-11-17 Size : 233kb User : wuyou
xinhaofashengqi Downloaded：0: Based on FPGA, QUARTUSS | | development environment to achieve adjustable signal generator can produce four kinds of wave
Date : 2025-11-17 Size : 1.21mb User : sujiebin
sin Downloaded：0: QUARTUSS | | environment simple sinusoidal signal generator, VERILOG code, use the embedded logic analyzer
Date : 2025-11-17 Size : 2.82mb User : sujiebin
D_latch Downloaded：0: ZLG ACTEl FPGA program to do a D flip-flop
Date : 2025-11-17 Size : 752kb User : 张金
HDL Downloaded：0: FPGA state machine design techniques
Date : 2025-11-17 Size : 118kb User : 张金

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