VHDL-FPGA-Verilog List Page 3024

VHDL-FPGA-Verilog list

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T1-add-strobe Downloaded：0: TI DaVinci cpld sources
Date : 2025-11-17 Size : 75kb User : Charlesliuc
vhdl Downloaded：0: Application of FPGA design training VHDL-RedLogic.pdf
Date : 2025-11-17 Size : 1.96mb User : 肖鑫
PULSE Downloaded：0: This is a group of parallel data to serial output 6 of the VHDL source code, with the external circuit can output positive and negative pulses, also with a logic diagram oh.
Date : 2025-11-17 Size : 7kb User : forget19
pingpongball Downloaded：0: Using VHDL language display VGA images directly into the CRT
Date : 2025-11-17 Size : 343kb User : 杨大伟
sodamachine Downloaded：0: Just finished an experiment, transfer up to share writing in general, please forgive the original question is a Massachusetts Institute of Technology EDA design problem: design a vending machine system, sold soda water,
Date : 2025-11-17 Size : 227kb User : Han
rs_decoder204_188 Downloaded：1: rs decoder verilog
Date : 2025-11-17 Size : 9.03mb User : songbing
crc Downloaded：0: CRC is use to detect whether the line right or wrong
Date : 2025-11-17 Size : 3.97mb User : 王良俊
8bitadder Downloaded：0: Serial 8-bit adder works have been compiled successfully
Date : 2025-11-17 Size : 296kb User : gaomeng
Huffman Downloaded：0: With the VHDL source code written in huffman coding
Date : 2025-11-17 Size : 10kb User : 孙敬峰
Uart Downloaded：0: Prepared with the Verilog source code to achieve UART interface
Date : 2025-11-17 Size : 4kb User : 孙敬峰
SOPC Downloaded：0: SOPC Quick Start Video
Date : 2025-11-17 Size : 41.54mb User : 123
VHDL Downloaded：0: EDA technology and VHDL" (version 2) courseware
Date : 2025-11-17 Size : 4.21mb User : 123

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