ZLG ACTEl FPGA program to do a D flip-flop

D锁存器实验例程及文档
.....................\D_latch
.....................\.......\component
.....................\.......\constraint
.....................\.......\coreconsole
.....................\.......\designer
.....................\.......\........\impl1
.....................\.......\........\.....\designer.log
.....................\.......\........\.....\D_latch.adb
.....................\.......\........\.....\D_latch.dtf
.....................\.......\........\.....\...........\verify.log
.....................\.......\........\.....\D_latch.ide_des
.....................\.......\........\.....\D_latch.pdb
.....................\.......\........\.....\D_latch.pdb.depends
.....................\.......\........\.....\D_latch.tcl
.....................\.......\........\.....\D_latch_fp
.....................\.......\........\.....\..........\D_latch.log
.....................\.......\........\.....\..........\D_latch.pro
.....................\.......\........\.....\..........\projectData
.....................\.......\........\.....\..........\...........\D_latch.pdb
.....................\.......\........\.....\simulation
.....................\.......\D_latch.prj
.....................\.......\hdl
.....................\.......\...\D_latch.v
.....................\.......\phy_synthesis
.....................\.......\simulation
.....................\.......\..........\modelsim.ini
.....................\.......\smartgen
.....................\.......\........\smartgen.aws
.....................\.......\stimulus
.....................\.......\synthesis
.....................\.......\.........\backup
.....................\.......\.........\coreip
.....................\.......\.........\D_latch.areasrr
.....................\.......\.........\D_latch.edn
.....................\.......\.........\D_latch.map
.....................\.......\.........\D_latch.pdc
.....................\.......\.........\D_latch.sdf
.....................\.......\.........\D_latch.so
.....................\.......\.........\D_latch.srd
.....................\.......\.........\D_latch.srm
.....................\.......\.........\D_latch.srr
.....................\.......\.........\D_latch.srs
.....................\.......\.........\D_latch.szr
.....................\.......\.........\D_latch.tlg
.....................\.......\.........\D_latch_sdc.sdc
.....................\.......\.........\D_latch_syn.prj
.....................\.......\.........\run_options.txt
.....................\.......\.........\stdout.log
.....................\.......\.........\syntmp
.....................\.......\.........\......\D_latch.plg
.....................\.......\viewdraw
.....................\.......\........\sch
.....................\.......\........\sym
.....................\.......\........\vf
.....................\.......\........\..\project.lst
.....................\.......\........\viewdraw.ini
.....................\.......\........\wir
.....................\D锁存器.pdf

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