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xinhaofashengqi

  • Category : VHDL-FPGA-Verilog
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  • Update : 2012-11-26
  • Size : 1.21mb
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  • Author :suji****
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Introduction - If you have any usage issues, please Google them yourself
Based on FPGA, QUARTUSS | | development environment to achieve adjustable signal generator can produce four kinds of wave
Packet file list
(Preview for download)
xinhaofashengqi\datarom.qip
...............\datarom.v
...............\datarom_bb.v
...............\datarom_wave0.jpg
...............\datarom_waveforms.html
...............\top.done
...............\top.fit.smsg
...............\top.fit.summary
...............\top.jdi
...............\top.map.summary
...............\top.mif
...............\top.pin
...............\top.pof
...............\top.qpf
...............\top.qsf
...............\top.sim.rpt
...............\top.sof
...............\top.tan.summary
...............\top.v
...............\top.v.bak
...............\top.vwf
...............\db\add_sub_lkc.tdf
...............\..\add_sub_mkc.tdf
...............\..\altsyncram_gm82.tdf
...............\..\altsyncram_kh91.tdf
...............\..\alt_u_div_mve.tdf
...............\..\decode_aoi.tdf
...............\..\lpm_divide_0dm.tdf
...............\..\mult_4s01.tdf
...............\..\top.map_bb.logdb
...............\..\prev_cmp_top.qmsg
...............\..\top.sgdiff.cdb
...............\..\sign_div_unsign_akh.tdf
...............\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.logdb
...............\..\top.sgdiff.hdb
...............\..\top.sld_design_entry_dsc.sci
...............\..\top.fit.qmsg
...............\..\top.cmp.logdb
...............\..\top.cmp.rdb
...............\..\top.map_bb.cdb
...............\..\top.map_bb.hdb
...............\..\top.map.logdb
...............\..\top.map.cdb
...............\..\top.map.hdb
...............\..\top.asm.qmsg
...............\..\top.cmp.hdb
...............\..\top.map.bpm
...............\..\top.asm_labs.ddb
...............\..\top.tan.qmsg
...............\..\prev_cmp_top.map.qmsg
...............\..\top.cmp0.ddb
...............\..\top.cmp.cdb
...............\..\top.cmp.ecobp
...............\..\prev_cmp_top.fit.qmsg
...............\..\top.cmp.bpm
...............\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.logdb
...............\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.dfp
...............\..\top.root_partition.cmp.logdb
...............\..\top.root_partition.cmp.dfp
...............\..\top.cmp.tdb
...............\..\top.eco.cdb
...............\..\top.tis_db_list.ddb
...............\..\top.atom.rvd
...............\..\top.cbx.xml
...............\..\prev_cmp_top.asm.qmsg
...............\..\top.signalprobe.cdb
...............\..\prev_cmp_top.tan.qmsg
...............\..\top.rpp.qmsg
...............\..\top.sgate.rvd
...............\..\top.sld_design_entry.sci
...............\..\top.db_info
...............\..\top.eds_overflow
...............\..\top.hier_info
...............\..\top.hif
...............\..\top.sgate_sm.rvd
...............\..\top.map.ecobp
...............\..\top.map_bb.hdbx
...............\..\top.psp
...............\..\top.root_partition.cmp.atm
...............\..\top.root_partition.cmp.hdbx
...............\..\top.root_partition.cmp.rcf
...............\..\top.root_partition.map.atm
...............\..\top.root_partition.map.hdbx
...............\..\top.sim.cvwf
...............\..\top.sim.hdb
...............\..\top.sim.qmsg
...............\..\top.sim.rdb
...............\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.atm
...............\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.cmp.hdbx
...............\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.atm
...............\..\top.sldhu_30e344a040fd07e1533c49de5f2d67d1.map.hdbx
...............\..\top.syn_hier_info
...............\..\top.tmw_info
...............\..\wed.wsf
...............\..\top.map.qmsg
...............\..\top.rtlv_sg.cdb
...............\..\top.rtlv.hdb
...............\..\top.rtlv_sg_swap.cdb
...............\..\top.pre_map.hdb
...............\..\top.pre_map.cdb
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