VHDL-FPGA-Verilog List Page 2700

VHDL-FPGA-Verilog list

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chuankou Downloaded：0: function of Serial Comunications
Date : 2025-11-21 Size : 2kb User : 海风
chengfaqi.doc Downloaded：0: Design a multiplier of two 5-digit multiplication. Enter the value with the light-emitting diode display, with 7-segment display shows the results. Multiplier and the multiplicand input twice (verilog language)
Date : 2025-11-21 Size : 362kb User : huanhuan
CPU Downloaded：0: 16-bit cpu with a simple VHDL language. There are several of the "
Date : 2025-11-21 Size : 3.03mb User : pjj
fir Downloaded：0: 11-order FIR digital filter
Date : 2025-11-21 Size : 1kb User : 重阳
circle Downloaded：0: VHDL routine to draw a circle using the midtpoint algorithm.
Date : 2025-11-21 Size : 2kb User : jcgcecilia
BeijingUniversityTutorialforVerilog Downloaded：0: Super detailed tutorial Verilog, hardware design, Department of Microelectronics, Peking University Tutorial.
Date : 2025-11-21 Size : 1.19mb User : 胡国平
DE2_lab_exercises Downloaded：0: DE2_labs_ exercise with verilog/vhdl
Date : 2025-11-21 Size : 1.51mb User : 电风扇
m_sequencer Downloaded：0: m sequence generator, the length can be varied. here the length of the shift register is 40. Feedback function : x40+ x5+ x4+ x3+1
Date : 2025-11-21 Size : 134kb User : 李雪茹
i2c_core_v02 Downloaded：0: I2C FPGA code to support master and slave
Date : 2025-11-21 Size : 4kb User : chen
das3580sch Downloaded：0: das3580 development board schematics, ■ Altera CycloneII EP2C8Q208C8N the FPGA device ■ EPCS4- 4Mbit serial configuration device ■ JTAG and AS dual-mode download port ■ 512Kbyte 10ns SRAM devices constitute a dual-level
Date : 2025-11-21 Size : 61kb User : 徐庆富
CPU Downloaded：0: Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
Date : 2025-11-21 Size : 6.3mb User : 涯
DlFIFO Downloaded：0: Fifo for everyone :)
Date : 2025-11-21 Size : 1kb User : Toan Nguyen

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