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VHDL-FPGA-Verilog list
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this is VHDL model of I2C_controller
Date : 2025-11-21 Size : 887kb User : Harshit B J

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this is source code in verilog for sequence controller and clock generator which is used in RISC cpu
Date : 2025-11-21 Size : 97kb User : Harshit B J

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this is source code in verilog for arithmatic logic unit for RISC cpu
Date : 2025-11-21 Size : 62kb User : Harshit B J

Altera FPGA Development Description (QuartusII 7.2 & ModelSim 6.5). Pdf project to establish and build QII QII pin assignment function simulation modelsim modelsim timing simulation (Altera simulation libraries establ
Date : 2025-11-21 Size : 2.9mb User :

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the introduction ISE for lilinx.
Date : 2025-11-21 Size : 598kb User : 张扬

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BCD Encoder (8421BCD), a very practical module
Date : 2025-11-21 Size : 2kb User : 张艳

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Cyclone II Device Family Data Sheet
Date : 2025-11-21 Size : 310kb User : maoyecheng

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library ieee use ieee.std_logic_arith.all use ieee.std_logic_1164.all use ieee.std_logic_unsigned.all entity PL_auto1 is port ( clk:in std_logic
Date : 2025-11-21 Size : 6kb User : Mr zhai

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232 to 485 circuits, the circuit to take power from the serial port, no external power supply
Date : 2025-11-21 Size : 34kb User : 王飞

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Using VHDL language design poc (parallel output controller) Usage: interrupt mode and query mode
Date : 2025-11-21 Size : 400kb User : 束佳云

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A minimum nios system implementation, very has reference value!
Date : 2025-11-21 Size : 18.14mb User : li

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Article describes how to download the FPGA ALTERA FGPA and the possible problems and solutions
Date : 2025-11-21 Size : 200kb User : 马雪峰
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