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VHDL-FPGA-Verilog list
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TestBench for stop_watch in VHDL
Date : 2025-11-22 Size : 4kb User : mmm

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test former partlelr list
Date : 2025-11-22 Size : 4kb User : Thiago

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This is the digital frequency meter, which is an experimental eda subject of course
Date : 2025-11-22 Size : 825kb User : phantom

Altera DDR SDRAM Controller. Verilog source codes, description documents, DDR verilog model and simulation testbench are all included.
Date : 2025-11-22 Size : 735kb User : 沈志

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SDH byte stream from the extracted E2 bytes, and the serial output in accordance with rates of E2 64K stream and clock, which clock 64K basic uniform requirements.
Date : 2025-11-22 Size : 1kb User : 魏可

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Design requirements: design of a vending machine. The system can complete the storage of goods, information, process control, coin handling, balance calculations, the LED functions. 4 kinds of goods can be managed, and t
Date : 2025-11-22 Size : 1kb User : DAVE

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MAXII
Date : 2025-11-22 Size : 605kb User : 刘洋

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Hello, vhdl program cycle shows, it is practical Oh, we have tried
Date : 2025-11-22 Size : 1kb User : yuan

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Simple decoder Design synthesized and loaded to board
Date : 2025-11-22 Size : 242kb User : verletzen

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String and convert to achieve, very easy to use, has been verified by simulation, you can.
Date : 2025-11-22 Size : 63kb User : yangxiao

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Vhdl code for sine wave generation, the output waveform standards, no significant waveform distortion.
Date : 2025-11-22 Size : 542kb User : yangxiao

it ia uart with all the features in it.
Date : 2025-11-22 Size : 128kb User : alpa c trivedi
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