VHDL-FPGA-Verilog List Page 2656

VHDL-FPGA-Verilog list

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hello Downloaded：0: VHDL language, design a platform in the DE2 8 segment digital tube display HELL0 program cycle, the speed control loop using keys, slow cycle time interval for the 1S, fast cycle time interval is 200ms.
Date : 2025-11-22 Size : 1kb User : chunyu
bakema Downloaded：0: eda platform, VHDL language design, design a Barker code generator.
Date : 2025-11-22 Size : 1kb User : chunyu
EDA Downloaded：0: eda: VHDL design with a seven-segment digital tube, led display in the 0- 9 numbers
Date : 2025-11-22 Size : 1kb User : chunyu
vhdl_practical Downloaded：0: vhdl practical book good reference for beginners
Date : 2025-11-22 Size : 123kb User : dskece
generate_fang Downloaded：0: CPLD generate the square wave function, can be changed to duty, in the experiment by EPM240.
Date : 2025-11-22 Size : 1kb User : A_Lai
ps2 Downloaded：0: PS2 break codes and pass codes 16 hex, for everybody to learn and improve together,
Date : 2025-11-22 Size : 1kb User : 李强
VHDLipinji2 Downloaded：0: This code is based FPGA software development environment, written by quartusII a sub-module of the overall procedure is not used to measure the frequency of 0-1000kz
Date : 2025-11-22 Size : 4kb User : qizi
EFY-HammingCode Downloaded：0: A vhdl source code for imlpementing hamming code
Date : 2025-11-22 Size : 209kb User : raja
1 Downloaded：0: VHDL design experiments based on VHDL-based design of experiments subject title
Date : 2025-11-22 Size : 4kb User : 孙林
Verilog_HDL Downloaded：0: verilog HDL programmed learning materials, on the basis of some help scholars
Date : 2025-11-22 Size : 8.23mb User :
CORDIC Downloaded：0: a document that explain clearly the cordic algorithm
Date : 2025-11-22 Size : 276kb User : sdfghj
S-35390A-IIC Downloaded：1: use the GPIO pin to simulate the IIC interface, based on the S-35390A RTC clock chipset command format, can send or receive single/multi byte command/data.
Date : 2025-11-22 Size : 1kb User : 陈朝炜

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